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• DCMR—This register controls the operation mode of the IDMA channel.
DCMR
BIT
0
1
2
FIELD
RESET
R/W
ADDR
Bits 0–10—Reserved
These bits are reserved and must be set to 0.
SIZE—Peripheral Port Size
00 = Word length.
01 = Half-word length.
10 = Byte length.
11 = Reserved.
TYPE—Source/Destination Type (Can Be Peripheral or Memory)
00 = Read and write from memory.
01 = Read from peripheral and write to memory.
10 = Read from memory and write to peripheral.
11 = Reserved.
SC—Single Cycle
0 = Dual-cycle mode.
1 = Single-cycle mode.
The following bits are only used by the RISC microcontroller:
• SAPR—This address pointer points to the next source data byte that IDMA transfers.
• DAPR—This address pointer points to the next destination byte that IDMA writes. When
the buffer descriptor is first processed, the communication processor module initializes
these pointers to the programmed values in the buffer descriptor.
• IBPTR—This pointer points to the next buffer descriptor that the IDMA transfers data to
when it is in idle state or points to the current buffer descriptor during transfer
processing. After a reset or when the end of an IDMA buffer descriptor table is reached,
the communication processor module initializes this pointer to the value programmed
in the IBASE register.
• WRITE_SP—This parameter must not be modified.
• S_BYTE_C—This parameter must not be modified.
• D_BYTE_C—This parameter must not be modified.
MOTOROLA
3
4
5
6
7
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x3CC2 (IDMA1) AND 0x3DC2 (IDMA2)
MPC823e REFERENCE MANUAL
Communication Processor Module
8
9
10
11
12
SIZE
0
R/W
13
14
15
TYPE
SC
0
0
R/W
R/W
16-93
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