Motorola MPC823e Reference Manual page 738

Communication Processor Module
DATA LENGTH
This field represents the number of bytes the SCCx ASYNC HDLC controller must transmit
from this buffer descriptor data buffer. It is never modified by the communication processor
module. The value of this field must be greater than zero. These bits are written by the SCCx
ASYNC HDLC controller after it finishes transmitting the associated data buffer.
TX DATA BUFFER POINTER
This field contains the address of the associated data buffer, can be even or odd, and can
reside in internal or external memory. The value of this field is never modified by the
communication processor module. These bits are written by the SCCx ASYNC HDLC
controller after it finishes transmitting the associated data buffer.
16.9.19.12.4 SCCx ASYNC HDLC Event Register. When a serial communication
controller is in asynchronous HDLC mode, the 16-bit memory-mapped SCCx event register
is referred to as the SCCx asynchronous HDLC event (SCCE–ASYNC HDLC) register.
Since each protocol has specific requirements, the SCCE bits are different for each
implementation. This register is used to generate interrupts and report events recognized by
the SCCx ASYNC HDLC channel. When an event is recognized, the SCCx ASYNC HDLC
controller sets the corresponding bit in the SCCE–ASYNC HDLC register. Interrupts
generated by this register can be masked by the SCCM–ASYNC HDLC register.
A bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be
cleared at a time. However, all unmasked bits must be cleared before the communication
processor module clears the internal interrupt request. This register is cleared at reset and
can be read at any time.
SCCE–ASYNC HDLC
BIT 0 1 2
FIELD
RESERVED
RESET
0
ADDR
Bits 0–2, 5–6, and 8—Reserved
These bits are reserved and must be set to 0.
GLR—Glitch on RX
If set, this bit indicates that a serial communication controller has found a glitch on the
receive clock.
GLT—Glitch on TX
If set, this bit indicates that a serial communication controller has found a glitch on the
transmit clock.
16-284
3 4 5 6 7
GLR GLT RESERVED IDL
0 0 0 0
(IMMR & 0xFFFF0000) + 0xA30
MPC823e REFERENCE MANUAL
8 9 10 11 12
RES BRKE BRKS TXE RXF
0 0 0 0 0
13 14 15
BSY TXB RXB
0 0 0
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