Motorola MPC823e Reference Manual page 1111

Development Capabilities and Interface
CHBMSK—Byte Mask for Comparator H
0000 = All bytes are not masked.
0001 = Last byte of the word is masked.
•
•
•
1111 = All bytes are masked.
Bits 30–31—Reserved
These bits are reserved and must be set to 0.
20.6.2.7 LOAD/STORE SUPPORT AND-OR CONTROL REGISTER. The load/store
support AND-OR control (LCTRL2) register is used to control the bit masks for load/store
data comparisons. Watchpoint programming consists of three control register fields—
LWxIA, LWxLA, and LWxLD. All three conditions must be detected to assert a watchpoint.
The reset value of this register is 0x00000000.
LCTRL2
BIT 0 1 2
LW0E
FIELD
LW0IA
N
RESET
0 0
R/W
R/W R/W
SPR
BIT 16 17 18
LW1L
FIELD
LW1LD
ADC
RESET
0 0
R/W
R/W R/W
SPR
LW0EN—First Load/Store Watchpoint Enable
0 = Watchpoint not enabled (reset value).
1 = Watchpoint enabled.
LW0IA—First Load/Store Watchpoint I-Address Watchpoint Selection
00 = First instruction watchpoint.
01 = Second instruction watchpoint.
10 = Third instruction watchpoint.
11 = Fourth instruction watchpoint.
20-50
3 4 5 6 7
LW0IA LW0L
LW0LA LW0LD
DC ADC
0 0 0 0
R/W R/W R/W R/W
157
19 20 21 22 23
LW1L BRKN
RESERVED
DDC OMSK
0 0
R/W R/W
157
MPC823e REFERENCE MANUAL
8 9 10 11 12
LW0L LW1E
LW1IA
DDC N
0 0 0
R/W R/W R/W
24 25 26 27 28
DLW0
EN
0 0
R/W R/W
13 14 15
LW1IA
LW1LA
DC
0 0
R/W R/W
29 30 31
DLW1 SLW0 SLW1
EN EN EN
0 0 0
R/W R/W R/W
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