Motorola MPC823e Reference Manual page 388

Memory Controller
As illustrated in Figure 15-6, the timing of the CSx signal is the same as the timing of the
address lines. The strobes for the transaction are supplied by the OE or WEx signals,
depending on the transaction direction (read or write). The negation of the WEx signal is
controlled by the CSNT bit of the ORx register. The CSx signal is generated when the ACS
field in the corresponding ORx register is set to '00'.
CLOCK
ADDRESS
TS
TA
CSx
WEx
OE
DATA
Figure 15-6. GPCM Memory Device Basic Timing
15-30
(ACS = 00, CSNT = 1, and TRLX = 0)
MPC823e REFERENCE MANUAL
CSNT = 1
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