Motorola MPC823e Reference Manual page 1089

Development Capabilities and Interface
20.4.2.4 SAVING THE MACHINE STATE IN DEBUG MODE. If entering debug mode is
the result of a load/store-type exception, the DAR and DSISR registers contain critical
information. These two registers must be saved before any other operation is performed.
Failing to save these registers can result in information loss if another load/store-type
exception occurs inside the development software. Since exceptions are treated differently
in debug mode, there is no need to save the SRR0 and SRR1 registers.
20.4.2.5 RUNNING IN DEBUG MODE. When running in debug mode, all fetch cycles
access the development port, regardless of the cycle's actual address. All load/store cycles
access the real memory system according to the cycle's address. The data register of the
development port is mapped as a special control register and is accessed using the mtspr
and mfspr instructions, via special load/store cycles.
Exceptions are treated differently in debug mode. When in debug mode, the ICR is updated
when an exception is recognized by the event that caused the exception. A special error
indication (ICR_OR) is asserted for one clock cycle to notify the development port that an
exception has occurred. Execution then continues in debug mode without any change in the
SRR0 and SRR1 registers. ICR_OR is asserted before the next fetch occurs so the
development system can detect the excepting instruction. However, not all exceptions are
recognizable in debug mode. Breakpoints and watchpoints are not generated by the
hardware when in debug mode, regardless of the MSR bit's value. When entering debug
RI
mode, the MSR bit is cleared by the hardware, thus forcing the hardware to ignore external
EE
and decrementer interrupts.
Caution: Setting the MSR bit with the debug software in debug mode is strictly
EE
forbidden.
This restriction is relevant because the external interrupt event is a level signal. Because the
core only reports exceptions in debug mode and does not perform exception processing, the
core hardware does not clear the MSR bit. This event, if enabled, is then recognized on
EE
every clock. When the ICR_OR signal is asserted, the development station must search the
ICR to find the event that caused the exception. Since the values in the SRR0 and SRR1
registers do not change if an exception is recognized in debug mode, they only change when
entering debug mode. However, it is not necessary to save the SRR0 and SRR1 registers
when entering debug mode.
20.4.2.6 EXITING DEBUG MODE. The rfi instruction is used to exit from debug mode and
return to normal processor operation and negate the FRZ signal. The development system
may monitor the FRZ signal or status to make sure the MPC823e is out of debug mode. It
is the software's responsibility to read the ICR before performing the rfi instruction. Failure
to do so forces the core to immediately reenter debug mode and reassert the freeze signal
if an asserted bit in the ICR register has a corresponding enable bit set in the DER register.
20-28 MPC823e REFERENCE MANUAL MOTOROLA