Page 1 MC68VZ328 Integrated Processor User’s Manual MC68VZ328UM/D Rev. 0, 02/2000...
Page 2 Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use...
Page 3: Table Of Contents
Features of the MC68VZ328 ........
Page 4 System Control Register ..........5-2 MC68VZ328 User’s Manual...
Page 5 5.2.2 Peripheral Control Register ......... . . 5-4 5.2.3 ID Register .
Page 6 Interrupt Control Register ..........9-8 MC68VZ328 User’s Manual...
Page 7 9.6.3 Interrupt Mask Register ..........9-10 9.6.4 Interrupt Status Register .
Page 8 Minute Stopwatch ..........11-4 viii MC68VZ328 User’s Manual...
Page 9 11.1.6.1 Minute Stopwatch Application Example ......11-4 11.2 Programming Model ........... 11-5 11.2.1 RTC Time Register .
Page 10 PWM Clock Signals ..........15-2 MC68VZ328 User’s Manual...
Page 11 15.2 PWM 1 ............. 15-2 15.3 PWM Operation .
Page 12 Register = 1) ..........19-27 MC68VZ328 User’s Manual...
Page 13 19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1) ..19-28 19.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1) ..19-29 19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS Latency = 1) .
Page 14 MC68VZ328 User’s Manual...
Page 15: List Of Figures
Figure 3-1 MC68VZ328 System Memory Map ........3-1 Figure 4-1 Clock Generation Module (CGM) Simplified Block Diagram .
Page 16 Figure 19-27 SPI 1 and SPI 2 Generic Timing Diagram ......19-32 MC68VZ328 User’s Manual...
Page 17 MC68VZ328 TQFP Pin Assignments—Top View ..... 20-2 Figure 20-2 MC68VZ328 TQFP Mechanical Drawing ......20-3 Figure 20-3 MC68VZ328 MAPBGA Pin Assignments—Top View.
Page 18 MC68VZ328 User’s Manual...
Page 19 List of Tables Table 1-1 Address Modes ..........1-6 Table 1-2 Instruction Set .
Page 20 Dedicated I/O Functions of Ports ........10-2 Table 10-2 MC68VZ328 I/O Port Status During the Reset Assertion Time Length ..10-4 Table 10-3 Pull-up and Pull-down Resistors by Port .
Page 21 Table 10-8 Port B Data Register Description ........10-9 Table 10-9 Port B Dedicated Function Assignments .
Page 22 Selected Baud Rate Settings ........14-9 Table 14-4 UART 1 Status/Control Register Description ......14-10 xxii MC68VZ328 User’s Manual...
Page 23 Table 14-5 UART 1 Baud Control Register Description ......14-12 Table 14-6 UART 1 Receiver Register Description ......14-13 Table 14-7 UART 1 Transmitter Register Description .
Page 24 Table 20-1 MC68VZ328 Ordering Information ....... . . 20-1 xxiv...
Page 25 List of Examples Example 4-1 Configuring the PLLCLK Frequency ....... . . 4-7 Example 4-2 Shutdown Example .
Page 26 MC68VZ328 User’s Manual...
Page 27: Audience
The MC68VZ328 user’s manual is intended to provide a design engineer with the necessary data to successfully integrate the MC68VZ328 into a wide variety of applications. It is assumed that the reader has a good working knowledge of the 68000 CPU. For programming information about the 68000, see the documents listed in the Suggested Reading section of this preface.
Page 28 Chapter 18 Application Guide: This chapter contains information that will assist during the integration of the MC68VZ328 into an existing or a new design. It includes a design checklist and instructions for using the MC68VZ328 Application Development System (ADS) board to get started with the design process.
Page 29: Suggested Reading
Suggested Reading The following documents are required for a complete description of the MC68VZ328 and are necessary to design properly with the part. Especially for those not familiar with the 68000 CPU, the following documents will be helpful when used in conjunction with this manual.
Page 30: Definitions, Acronyms, And Abbreviations
MAPBGA mold array process ball grid array MIPS million instructions per second pulse-width modulator real-time clock system integration module serial peripheral interface SRAM static RAM TQFP thin quad flat pack UART universal asynchronous receiver/transmitter XTAL crystal MC68VZ328 User’s Manual...
Page 31: Introduction
Introduction This chapter describes the overall system architecture of the MC68VZ328 (DragonBall™ VZ) integrated processor. It provides an overview of the 68000 CPU and the operational blocks of the MC68VZ328 at a system level. The MC68VZ328 builds on the success of the earlier DragonBall processors and features a synthesizable 68000 core that utilizes an advanced process technology.
Page 32: Features Of The Mc68Vz328
Features of the MC68VZ328 Figure 1-1. MC68VZ328 Block Diagram Features of the MC68VZ328 The features of the DragonBall VZ include the following: • Static FLX68000 CPU—identical to the MC68EC000 microprocessor — Full compatibility with MC68000 and MC68EC000 — 32-bit internal address bus —...
Page 33 — Software-programmable screen size (up to 640 and color STN panels — Capability of directly driving popular LCD drivers and modules from Motorola, Sharp, Hitachi, Toshiba, and numerous other manufacturers — Support for up to 16 gray levels out of a palette of 16 density levels —...
Page 34: Cpu
— Operating voltage of 2.7 V to 3.3 V — Compact 144-lead thin quad flat pack (TQFP) and MAPBGA The FLX68000 CPU in the MC68VZ328 is an updated implementation of the 68000 32-bit microprocessor architecture. The main features of the CPU are the following: •...
Page 35: Cpu Programming Model
1.2.1 CPU Programming Model The CPU has 32-bit registers and a 32-bit program counter, which are shown in Figure 1-2. The first eight registers (D7–D0) are data registers that are used for byte (8-bit), word (16-bit), and long-word (32-bit) operations. When being used to manipulate data, the data registers affect the status register (SR). The next seven registers (A6–A0) and the user stack pointer (USP) can function as software stack pointers and base address registers.
Page 36: Data And Address Mode Types
These instructions, shown in Table 1-2 on page 1-7, include signed and unsigned multiply and divide, quick arithmetic operations, binary-coded decimal (BCD) arithmetic, and expanded operations (through traps). Table 1-1. Address Modes SR/USP/SP/PC MC68VZ328 User’s Manual Syntax xxx.W xxx.L (PC)
Page 37: Table 1-2 Instruction Set
Mnemonic Description ABCD Add decimal with extend ADDA Add address ADDQ Add quick ADDI Add immediate ADDX Add with extend Logical AND ANDI AND immediate ANDI to CCR AND immediate to condition codes ANDI to SR AND immediate to status register Arithmetic shift left Arithmetic shift right Branch conditionally...
Page 38: Modules Of The Mc68Vz328
Modules of the MC68VZ328 Table 1-2. Instruction Set (Continued) Mnemonic Description EORI Exclusive OR immediate EORI to CCR Exclusive OR immediate to condition codes EORI to SR Exclusive OR immediate to status register Exchange registers Sign extend Jump Jump to subroutine...
Page 39: System Control
1.3.4 Chip-Select Logic The MC68VZ328 provides eight programmable general-purpose chip-select signals to allow the selection of a wide variety of memory or external peripherals. Each chip-select signal provides a write-protect option, internal and external DTACK generation, and 8-bit and 16-bit data port size selection. For more detailed information about using the chip-select logic, see Chapter 6, “Chip-Select Logic.”...
Page 40: General-Purpose I/O (Gpio) Lines
General-Purpose Timer The MC68VZ328 has two 16-bit timers that can be used in various modes to capture the timer value with an external event, to trigger an external event or interrupt when the timer reaches a set value, or to count external events.
Page 41: Pulse-Width Modulators (Pwm)
Chapter 14, “Universal Asynchronous Receiver/Transmitter 1 and 2,” for information on operating and programming the UART controllers. Once a program is downloaded to the MC68VZ328, it can be executed, providing a simple debugging environment for failure analysis and a channel to update programs stored in flash memory.
Page 42 Modules of the MC68VZ328 1-12 MC68VZ328 User’s Manual...
Page 43: Signal Descriptions
This chapter describes the MC68VZ328’s input and output signals, which are organized into functional groups, as illustrated in Figure 2-1 on page 2-2. The MC68VZ328 uses a standard M68000 bus to communicate with on-chip and external peripherals. This single continuous bus exists both on and off the chip.
Page 44: Signals Grouped By Function
Real-Time RESET Processor PG2/EMUIRQ Emulation PG3/HIZ/P/D PG4/EMUCS PG5/EMUBRK Figure 2-1. Signals Grouped by Function Signals Grouped by Function Table 2-1 on page 2-3 groups the MC68VZ328 signals according to their function. Voltage Regulator Static Memory Controller 8/16-Bit Chip-Select 68000 Interface...
Page 45: Table 2-1 Signal Function Groups
Table 2-1. Signal Function Groups Function Group Power Ground Regulator output Clocks/PCIO XTAL, EXTAL, CLKO/PF2 System control RESET Address bus/PFIO PF[3:6]/A[23:20], A[19:14], A0/PG1, MA[15:0]/A[16:1] Lower data bus/PAIO PA[7:0]/D[7:0] Upper data bus D[15:8] Bus control/PCIO/PEIO/ BUSW/DTACK/PG0, OE, LWE/LB, UWE/UB, PKIO PE3/DWE/UCLK, PK2/LDS, PK3/UDS, PK1/RW Interrupt controller/PMIO INT0/PD0, INT1/PD1, INT2/PD2, INT3/PD3, IRQ1/PD4, IRQ2/PD5, IRQ3/PD6, IRQ6/PD7,...
Page 46: Power And Ground Signals
RESET—Reset. This active low, Schmitt trigger input signal resets the entire MC68VZ328 processor (CPU and peripherals). The threshold of this Schmitt trigger device is 1.2 V high and 0.8 V low. After the MC68VZ328 powers up, this reset input signal should be driven low for at least µ...
Page 47: Address Bus Signals
Port F. These signals default to address functions after reset. Data Bus Signals The flexible data bus interface design of the MC68VZ328 microprocessor allows programming of the lower byte of the data bus (in an 8-bit-only system) to operate as general-purpose I/O signals. In sleep mode, all of the data bus pins (D15–D0) are individually pulled up with 1-megaohm resistors.
Page 48: Bus Control Signals
Interrupt Controller Signals Bus Control Signals The bus control signals are used for both the configuration and operation of the MC68VZ328 bus. The following descriptions provide detailed information about programming the signals and their use. • LWE/LB, UWE/UB—Lower Byte Write-Enable and Upper Byte Write-Enable, or Lower Byte and Upper Byte data strobes.
Page 49: Lcd Controller Signals
ICEMSR. See Section 9.6.4, “Interrupt Status Register,” on page 9-12 for more information. LCD Controller Signals The MC68VZ328 contains all necessary circuitry to support an external LCD display panel. This section describes the signals used by the LCD controller. It also provides some programming information about the use of these signals.
Page 50: Uart 1 And Uart 2 Controller Signals
These pins default to GPIO input pulled high. 2.10 Timer Signals There are several external timer and clock signal functions available using the MC68VZ328. This section describes the signals and how they are programmed. •...
Page 51: Pulse-Width Modulator Signals
(DATA_READY) is selected. This pin defaults to GPIO input pulled high. 2.12 Serial Peripheral Interface 1 Signals There are two serial peripheral interface (SPI) modules in the MC68VZ328. This section describes the signals that are used with SPI 1 to interface with external devices. •...
Page 52: Chip-Select And Edo Ram Interface Signals
PM1/SDCE—Port M bit 1 or SDRAM Clock Enable. This pin defaults to GPIO pulled low. • PM2/DQMH, PM3/DQML—Port M bits 2–3 or SDRAM input/output mask. These pins default to GPIO pulled low. • PM4/SDA10—Port M bit 4 or SDRAM Address A10. This pin defaults to GPIO input pulled low. 2-10 MC68VZ328 User’s Manual...
Page 53: In-Circuit Emulation (Ice) Signals
HIZ/P/D/PG3—High Impedance, Program/Data, or Port G bit 3. During system reset, a logic low of this input signal will put the MC68VZ328 into Hi-Z mode, in which all MC68VZ328 pins are three-stated after reset release. For normal operation, this pin must be pulled high during system reset or left unconnected.
Page 54 In-Circuit Emulation (ICE) Signals 2-12 MC68VZ328 User’s Manual...
Page 55: Memory Map
Supervisor Memory Map Monitor Program (Defined by User) System Memory 0x1FFFFFFF 0xFFFC0000 Emulator 0xFFFDFFFF 0xFFFFF000 0xFFFFFDff 0xFFFFFF00 0xFFFFFfff Figure 3-1. MC68VZ328 System Memory Map 512 Mbyte Monitor Reserved MC68VZ328 Register Bootstrap Memory Map User’s Memory Map Program / Data Memory...
Page 56: Programmer's Memory Map
Emulation chip-select register PLL control register PLL frequency select register — Reserved Power control register Interrupt vector register Interrupt control register Interrupt mask register Reserved Interrupt status register MC68VZ328 User’s Manual Page Reset Value Number 0x1C 0x00 0x56000000 0x1FFF 0x0000 0x0000 0x0000...
Page 57 Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued) Address Name Width 0xFFFFF310 0xFFFFF314 ILCR 0xFFFFF400 PADIR 0xFFFFF401 PADATA 0xFFFFF402 PAPUEN 0xFFFFF403 0xFFFFF408 PBDIR 0xFFFFF409 PBDATA 0xFFFFF40A PBPUEN 0xFFFFF40B PBSEL 0xFFFFF410 PCDIR 0xFFFFF411 PCDATA 0xFFFFF412 PCPDEN 0xFFFFF413 PCSEL 0xFFFFF418 PDDIR 0xFFFFF419 PDDATA 0xFFFFF41A...
Page 58 PWM unit 1 period register PWM unit 1 counter register Reserved PWM unit 2 control register PWM unit 2 period register PWM unit 2 width register PWM unit 2 counter register MC68VZ328 User’s Manual Page Reset Value Number 0xFF 10-27 0x87...
Page 59 Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued) Address Name Width 0xFFFFF600 TCTL1 0xFFFFF602 TPRER1 0xFFFFF604 TCMP1 0xFFFFF606 TCR1 0xFFFFF608 TCN1 0xFFFFF60A TSTAT1 0xFFFFF610 TCTL2 0xFFFFF612 TPRER2 0xFFFFF614 TCMP2 0xFFFFF616 TCR2 0xFFFFF618 TCN2 0xFFFFF61A TSTAT2 0xFFFFF700 SPIRXD 0xFFFFF702 SPITXD 0xFFFFF704 SPICONT1 0xFFFFF706...
Page 60 LCD refresh rate adjustment register Reserved LCD panning offset register LCD frame rate control modulation register LCD gray palette mapping register PWM contrast control register Refresh mode control register DMA control register MC68VZ328 User’s Manual Page Reset Value Number 0x003F 14-12 0x0000 14-13 0x0000...
Page 61 Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued) Address Name Width 0xFFFFFB00 RTCTIME 0xFFFFFB04 RTCALRM 0xFFFFFB0A WATCHDOG 0xFFFFFB0C RTCCTL 0xFFFFFB0E RTCISR 0xFFFFFB10 RTCIENR 0xFFFFFB12 STPWCH 0xFFFFFB1A DAYR 0xFFFFFB1C DAYALARM 0xFFFFFC00 DRAMMC 0xFFFFFC02 DRAMC 0xFFFFFC04 SDCTRL 0xFFFFFC06 SDPWDN 0xFFFFFC80 0xFFFFFD00 ICEMACR 0xFFFFFD04 ICEMAMR...
Page 62 ICEM address mask register ICEM control compare register ICEM control mask register ICEM control register ICEM status register Interrupt control register Silicon ID register Interrupt level control register Interrupt mask register MC68VZ328 User’s Manual Page Reset Value Number — — 0x00B0 0x0000 0x0000...
Page 63 Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued) Name Address Width IODCR 0xFFFFF008 0xFFFFF310 0xFFFFF30C 0xFFFFF300 LACDRC 0xFFFFFA23 LBLKC 0xFFFFFA1F LCKCON 0xFFFFFA27 LCWCH 0xFFFFFA1C LCXP 0xFFFFFA18 LCYP 0xFFFFFA1A LFRCM 0xFFFFFA31 LGPMR 0xFFFFFA33 LPICF 0xFFFFFA20 LPOLCF 0xFFFFFA21 LPOSR 0xFFFFFA2D LPXCD 0xFFFFFA25 LRRA...
Page 64 Port F data register Port F direction register Port F pull-up/pull-down enable register Port F select register Port G data register Port G direction register Port G pull-up enable register MC68VZ328 User’s Manual Page Reset Value Number 0x00 10-8 0xFF 10-8...
Page 65 Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued) Name Address Width PGSEL 0xFFFFF433 PJDATA 0xFFFFF439 PJDIR 0xFFFFF438 PJPUEN 0xFFFFF43A PJSEL 0xFFFFF43B PKDATA 0xFFFFF441 PKDIR 0xFFFFF440 PKPUEN 0xFFFFF442 PKSEL 0xFFFFF443 PLLCR 0xFFFFF200 PLLFSR 0xFFFFF202 PMDATA 0xFFFFF449 PMDIR 0xFFFFF448 PMPUEN 0xFFFFF44A PMSEL 0xFFFFF44B...
Page 66 Timer unit 1 counter register Timer unit 2 counter register Timer unit 1 capture register Timer unit 2 capture register Timer unit 1 control register Timer unit 2 control register MC68VZ328 User’s Manual Page Reset Value Number — — —...
Page 67 Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued) Name Address Width TPRER1 0xFFFFF602 TPRER2 0xFFFFF612 TSTAT1 0xFFFFF60A TSTAT2 0xFFFFF61A UBAUD1 0xFFFFF902 UBAUD2 0xFFFFF912 UMISC1 0xFFFFF908 UMISC2 0xFFFFF918 URX1 0xFFFFF904 URX2 0xFFFFF914 USTCNT1 0xFFFFF900 USTCNT2 0xFFFFF910 UTX1 0xFFFFF906 UTX2 0xFFFFF916 WATCHDOG 0xFFFFFB0A...
Page 68 Programmer’s Memory Map 3-14 MC68VZ328 User’s Manual...
Page 69: Clock Generation Module And Power Control Module
The PCM controls the power consumption of the CPU by applying clock signals to the CPU at reduced burst widths. For maximum power savings, the MC68VZ328 can be placed in sleep mode in which all clocks (except for the low-frequency clock) are disabled.
Page 70: Introduction To The Clock Generation Module
CLK32 signal, the frequency of the clock signals can be individually programmed. Table 4-1. CGM Clock Signal Distribution Used by or Available To CLKO/PF2 pin DRAM controller LCD controller SPIs Timers UARTs CLK32 SYSCLK DMACLK MC68VZ328 User’s Manual LCDCLK...
Page 71: Cgm Operational Overview
2 (PRESC2) bit in the PLLCR. The DMACLK signal is applied to the LCD controller in the MC68VZ328 and also serves as the clock source for the LCD clock divider and the SYSCLK divider. The output of the LCD clock divider is LCDCLK, whose frequency is controlled by the LCD clock selection (LCDCLK) field in the PLLCR.
Page 72: Detailed Cgm Clock Descriptions
Regardless of the crystal frequency used, the output is always labeled CLK32. Figure 4-2 represents a suggestion of how a crystal may be connected to the MC68VZ328. The values of C1 and C2 in Figure 4-2 are determined by using the crystal load capacitance (CL), PCB stray capacitance, Cstray (measured or approximated), and DragonBall input capacitance (Cdbvz <<...
Page 73: Pllclk Initial Power-Up Sequence
Refer to Figure 4-3 for a graphical representation of the following power-up sequence description. When power is initially applied to the MC68VZ328, the XTAL oscillator begins to oscillate. Due to the low-power design on the oscillator pads, the RESET signal must be asserted (low) for at least 1.2 s to ensure that the crystal oscillator starts and stabilizes.
Page 74: Pll Frequency Selection
In Example 4-1, the variable NEWFREQ is the new frequency value (P and Q values) to be programmed. The MC68VZ328 is placed in sleep mode before the stop command. See Section 4.5.1.4, “Sleep Mode,” for detailed information about sleep modes. This routine enables the timer to wake up the PLL after 96 CLK32 periods.
Page 75: Programming Considerations When Changing Frequencies
PLL control register, which places the chip in sleep mode. See Section 4.5.1.4, “Sleep Mode,” for more details. When the MC68VZ328 is awakened from sleep mode by a wake-up event, the PLL output (PLLCLK) is available after a delay determined by the setting in the WKSEL field of PLLCR.
Page 76: Cgm Programming Model
1 = PLLCLK ÷ 2 (default). This bit is reserved and should be set to 0. 0 = PR1CLK ÷ 1. 1 = PR1CLK ÷ 2 (default). 0 = CLKO enabled. 1 = CLKO disabled (default). MC68VZ328 User’s Manual 0xFFFFF200 CLKEN DISPLL WKSEL Setting...
Page 77: Table 4-3 Wksel Field (Pllcr) Delay Settings
Table 4-2. PLL Control Register Description (Continued) Name Description DISPLL Disable PLL—This bit, when set, disables the Bit 3 output of the PLL, placing the chip in sleep mode, its lowest power state. Reserved Reserved Bit 2 WKSEL Wake-up Clock Select—This field selects the Bits 1–0 delay of the PLL output from the initiation of the wake up until an output is available.
Page 78: Pll Frequency Select Register
MC68VZ328, so to conserve power while the CPU is relatively idle, the PCM can disable the CPU clock or apply the clock in bursts. When the MC68VZ328 is in one of these reduced-power modes, it is restored to normal operation by a wake-up event. When this occurs, the clock is immediately enabled, allowing the CPU to service the request.
Page 79: Operating The Pcm
The power control module has four modes of operation: normal, burst, doze and sleep. In normal mode, the PCM is off. The MC68VZ328 enters burst mode when the PCM is enabled. In burst mode, the PCM controls the burst width of the CPUCLK signal to the CPU. If the burst width of the CPU clock is reduced to zero, CPUCLK is disabled and the MC68VZ328 is in doze mode.
Page 80: Sleep Mode
Sleep Mode Unlike burst or doze mode, sleep mode disables all of the clocks in the MC68VZ328 with the exception of the CLK32. The output of the PLL in the CGM is disabled in sleep mode through setting the DISPLL bit in the PLLCR register.
Page 81: Figure 4-4 Power Control Module Block Diagram
CLK32 SYSCLK PCTLR Figure 4-4. Power Control Module Block Diagram If a wake-up event occurs while CPUCLK is disabled, the PCM is disabled and CPUCLK is immediately restored, allowing the CPU to process the event. The DMA controller always has priority, so if a DMA access is in progress, the CPU will wait until the DMA controller has completed its access before servicing the wake-up routine.
Page 82: Power Control Register
These bits are reserved and should remain set to 0. 00000 = 0/31 clock burst width. 00001 = 1/31 clock burst width. 00010 = 2/31 clock burst width. 11111 = 31/31 clock burst width. MC68VZ328 User’s Manual 0x(FF)FFF207 BIT 0 WIDTH Setting...
Page 83: System Control
The BETO bit in the system control register is set after a bus time out, which may indicate a write-protect violation or privilege. The watchdog timer resets the MC68VZ328 if it is enabled and not cleared or disabled before reaching terminal count. The watchdog timer is enabled at reset.
Page 84: Table 5-1 System Control Register Description
1 = A privilege violation has occurred. 0 = Disable the bus error timer. 1 = Enable the bus error timer. 0 = User and supervisor mode. 1 = Supervisor-only mode. MC68VZ328 User’s Manual 0x(FF)FFF000 BIT 0 DMAP WDTH8 Setting...
Page 85 Table 5-1. System Control Register Description (Continued) Name Description DMAP Double Map—This control bit controls the Bit 2 double-mapping function. Reserved Reserved Bit 1 WDTH8 8-Bit Width Select—This control bit allows the Bit 0 D[7:0] pins to be used for Port A input/output. 0 = The on-chip registers are mapped at 0xFFFFF000–0xFFFFFFFF.
Page 86: Peripheral Control Register
(DIR6 = 0), or TOUT -> Timer 1 (DIR6 = 1). 11 = Timer 1 OUT -> Timer 2 IN; TIN -> Timer 1 (DIR6 = 0), or TOUT -> Timer 2 (DIR6 = 1). MC68VZ328 User’s Manual 0x(FF)FFF003 BIT 0...
Page 87: Id Register
5.2.3 ID Register This 32-bit read-only register shows the chip identification. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 5-3. BIT 31 CHIPID TYPE RESET BIT 15...
Page 88: I/O Drive Control Register
I/O Drive Control Register 0x1FFF Description MC68VZ328 User’s Manual 0x(FF)FFF008 BIT 0 Setting Do not use these bits. 0 = I/O drive current for each pin is 2 mA.
Page 89: Chip-Select Logic
Overview of the CSL The MC68VZ328 microprocessor contains eight general-purpose, programmable chip-select signals, which are used to select external devices on the address and data bus. The signals are arranged in four groups of two—CSA[1:0], CSB[1:0], CSC[1:0], and CSD[1:0].
Page 90: Chip-Select Operation
ROM, SRAM, flash memory chip ROM, SRAM, flash memory chip ROM, SRAM, flash memory chip DRAM, ROM, SRAM, flash memory chip-select DRAM, ROM, SRAM, flash memory chip-select DRAM, ROM, SRAM, flash memory chip-select DRAM, ROM, SRAM, flash memory chip-select NOTE: MC68VZ328 User’s Manual...
Page 91: Programmable Data Bus Size
Chip-Select Operation chip-select–controlled area can be programmed as read/write, which provides optimal memory use, as shown in Figure 6-1. This area can be defined by programming the UPSIZ bits in the CSB, CSC, and CSD registers to between 32K and the entire chip-select area. Unprotected Memory (Read/Write) Up to 4 Mbyte CSB0...
Page 92: Overlapping Chip-Select Registers
0x0000 The chip-select base address must be set according to the size of the corresponding chip-select signals of the group. This bit is reserved and should be set to 0. MC68VZ328 User’s Manual × × × 0, 0 4 Mbyte, 0 8 Mbyte, ×...
Page 93: Table 6-3 Chip-Select Group B Base Address Register Description
CSGBB Chip-Select Group B Base Address Register TYPE RESET Table 6-3. Chip-Select Group B Base Address Register Description Name Description GBBx Group B Base Address – Bits 15 the high-order bits (28–14) of the starting address for the chip-select range. Reserved Reserved Bit 0...
Page 94: Chip-Select Upper Group Base Address Register
This bit is reserved and should be set to 0. BGBA[31:29] CGBA[31:29] 0x0000 0 = Ignores A31, A30, and A29. 1 = Decoding includes A31, A30, and A29. Enter value for bits 31–29 of chip-select regis- ter A. MC68VZ328 User’s Manual 0x(FF)FFF106 Setting 0x(FF)FFF108 DGBA[31:29] Setting...
Page 95 Table 6-6. Chip-Select Upper Group Base Address Register Description (Continued) Name Description Reserved Reserved Bit 11 BGBA[31:29] MSB for Chip-Select B—The upper most sig- Bits 10–8 nificant bits for chip-select group B base address. The value will be ignored if UGEN is disabled.
Page 96: Chip-Select Registers
110 = 12 + WS0 wait states. 111 = External DTACK. When using the external DTACK signal, you must select DTACK function in Port G. WS0 is the DWS0, CWS0, BWS0, or AWS0 bit in the CSCTRL1 register. MC68VZ328 User’s Manual 0x(FF)FFF110 WS3–1 Setting...
Page 97 Table 6-7. Chip-Select Register A Description (Continued) Name Description Chip-Select Size—This field determines the Bits 3–1 memory range of the chip-select. For CSAx and CSBx, the chip-select size is between 128K and 16 Mbyte. For CSCx and CSDx, the chip-select size is between 32K and 16 Mbyte. Chip-Select Enable—This write-only bit Bit 0 enables each chip-select.
Page 98: Table 6-8 Chip-Select Register B Description
These bits are reserved and should be set to 0. 0 = The chip-select and LWE/UWE signals go active at the same clock edge. 1 = The chip-select signal goes low 1 clock before LWE/UWE. 0 = 8 bit. 1 = 16 bit. MC68VZ328 User’s Manual 0x(FF)FFF112 WS3–1 Setting...
Page 99 Table 6-8. Chip-Select Register B Description (Continued) Name Description WS3–1 Wait State—This field determines the Bits 6–4 number of wait states added before an internal DTACK signal is returned for this chip-select. Note: When using the external DTACK signal, you must configure the BUSW/DTACK/PG0 pin.
Page 100: Table 6-9 Chip-Select Register C Description
These bits are reserved and should be set to 0. 0 = The chip-select and LWE/UWE signals go active at the same clock edge. 1 = The chip-select signal goes low 1 clock before LWE/UWE. 0 = 8 bit. 1 = 16 bit. MC68VZ328 User’s Manual 0x(FF)FFF114 WS3–1 Setting...
Page 101 Table 6-9. Chip-Select Register C Description (Continued) Name Description WS3–1 Wait State—This field determines the Bits 6–4 number of wait states added before an internal DTACK signal is returned for this chip-select. Note: When using the external DTACK signal, you must configure the BUSW/DTACK/PG0 pin.
Page 102: Table 6-10 Chip-Select Register D Description
10 = 128K. 11 = 256K. 0 = RAS0 to RAS0 memory space. 1 = RAS0 covers both RAS0 and RAS1 memory space B. 0 = Select CSC[1:0] and CSD[1:0]. 1 = Select CAS and RAS. MC68VZ328 User’s Manual 0x(FF)FFF116 WS3–1 Setting...
Page 103 Table 6-10. Chip-Select Register D Description (Continued) Name Description FLASH Flash Memory Support—When enabled, Bit 8 this bit provides support for flash memory by forcing the LWE/UWE signal to go active after chip-select. Note: This bit is used for expanded memory size for CSD when the DRAM bit is enabled.
Page 104: Emulation Chip-Select Register
6.3.4 Emulation Chip-Select Register In addition to the eight general-purpose chip-select signals, the MC68VZ328 has an emulation chip-select register (EMUCS) that is specifically designed for the in-circuit emulation module. This register provides wait states 12–0, depending on the type of chip used. External logic (DTACK) may also be used to have longer wait states.
Page 105: Table 6-12 Chip-Select Control Register 1 Description
CSCTRL1 Chip-Select Control Register 1 BIT 15 TYPE RESET Table 6-12. Chip-Select Control Register 1 Description Name Description Reserved Reserved Bit 15 EUPEN Extra UPSIZ Bit Enable—This bit enables the Bit 14 BUPS2, CUPS2, and DUPS2 bits to work with the corresponding UPSIZ configuration bits.
Page 106: Chip-Select Control Register 2
This bit is reserved and should be set to 0. For information on calculating unprotected memory size, see Example 6-1. Chip-Select Size --------------------------------------- - 7 UPSIZ – EASP EASDLY[1:0] 0x1000 0 = Disabled. 1 = Enabled. MC68VZ328 User’s Manual Setting 0x(FF)FFF10C BIT 0 Setting...
Page 107 Table 6-13. Chip-Select Control Register 2 Description (Continued) Name Description ECDS Early Cycle Detection for Static Bit 14 Memory—This bit advances the chip-select signals for SRAM, ROM, or flash memory. It allows more setup time for slow memory with- out adding CPU wait states. ECDT Early Cycle Detection Type—When the mas- Bit 13...
Page 108: Chip-Select Control Register 3
1 = Enable DS toggling between two 8-bit transfers. 0 = Disable CS toggling between two 8-bit transfers. 1 = Enable CS toggling between two 8-bit transfers. These bits are reserved and should be set to MC68VZ328 User’s Manual 0x(FF)FFF150 BIT 0 Setting...
Page 109 Example 6-2. Programming Example ************************************************ Chip-Select registers ************************************************ REGSBASE 0xFFFFF000internal registers base address BASEA REGSBASE+0x100 BASEB REGSBASE+0x102 BASEC REGSBASE+0x104 BASED REGSBASE+0x106 REGSBASE+0x110 REGSBASE+0x112 REGSBASE+0x114 REGSBASE+0x116 ************************************************ PORT control registers ************************************************ PORTBASE REGSBASE+0x400 port B registers base address PBDir PORTBASE+0x08 port B direction register PBData PORTBASE+0x09 port B data register PBPU...
Page 110 Programming Model 6-22 MC68VZ328 User’s Manual...
Page 111: Dram Controller
Chapter 7 DRAM Controller This chapter describes the DRAM controller for the MC68VZ328. The operation of the DRAM controller is closely linked to the chip-select logic. Please refer to Chapter 6, “Chip-Select Logic,” for more details. Introduction to the DRAM Controller The DRAM controller provides a glueless interface for either 8-bit or 16-bit DRAM.
Page 112: Figure 7-1 Dram Controller Block Diagram
Address Data Control CSD0 CSD1 Page Access (from LCD) 8-Bit Port (from SIM) A[31:1] Figure 7-1. DRAM Controller Block Diagram Mode Control Refresh Control DRAM Signal Control DTACK Control DRAM Address Control MC68VZ328 User’s Manual RAS0 RAS1 CAS0 CAS1 MD[15:0]...
Page 113: Dram Controller Operation
PA[9:1], and PA[19:10] is used for the row addresses. The address multiplexing options are provided in Table 7-1 on page 7-4. The MC68VZ328’s DRAM controller uses PA[8:1] as the column addresses for MD[7:0] and then allows software to select either PA0 or PA9 for column address MD8.
Page 114: Table 7-1 Dram Address Multiplexing Options
A13/MD12 PA19 PA20 PA10 PA21 PA22 PA21 PA23 PA12 PA13 PA11 PA20 PA10 PA22 PA21 PA23 MD10 MD11 MD12 MC68VZ328 User’s Manual A6/MD5 A7/MD6 A8/MD7 PA16 PA17 PA18 A14/MD13 A15/MD14 A16/MD15 PA22 PA23 PA24 PA22 PA23 PA24 PA22 PA23 PA24...
Page 115: Table 7-2. 16 Mbit Sdram-256 (16-Bit) And 512 (8-Bit) Page Size
Table 7-2 through Table 7-5 on page 7-6 provide recommendations for MC68VZ328–to–SDRAM connections and for selecting multiplexing options for different types of SDRAM. Table 7-2. 16 Mbit SDRAM—256 (16-Bit) and 512 (8-Bit) Page Size SDRAM Pins VZ Pins PA11 PA12...
Page 116: Table 7-4. 128 Mbit Sdram-512 (16-Bit) And 1024 (8-Bit) Page Size
Table 7-5. 256 Mbit SDRAM—512 (16-Bit) and 1024 (8-Bit) Page Size SDRAM Pins VZ Pins Address Options Column Address Options (16-Bit) Column Address Options (8-Bit) Note: X = “don’t care” MC68VZ328 User’s Manual A12/ A15/ PA22 PA23 PA22 PA23 PA22 PA23...
Page 117: Dtack Generation
7.2.3 Refresh Control During normal operation, the MC68VZ328 DRAM cycles are distributed evenly over the refresh period. The DRAM refresh rate requirement may vary between different DRAM chips. Users can program the REF field in the DRAM configuration register (DRAMMC) to select the required refresh frequency.
Page 118: Lcd Interface
LCD controller’s access cycle. In this mode, the DRAM controller supports page accesses. Controller Figure 7-2. LCD Controller and DRAM Controller Interface PAGE_ACCESS DTACK DRAM Controller Address Data MC68VZ328 User’s Manual MD[12:0] External Address External Data...
Page 119: 8-Bit Mode
7.2.5 8-Bit Mode From the system integration module (SIM), 8-bit operation on the fly can be selected using the signal 8-bit port. If one of the CSDx signals is programmed as 8-bit mode, the 8-bit mode signal will be active at the same time that CSDx is active.
Page 120: Data Retention During Reset
Refresh 15.6 µs CPCRESET DRAM Reset Port (CSCx, CSDx) Reset System Clock Sleep with No SYSCLK Figure 7-3. Data Retention for the Reset Cycle 7-10 MC68VZ328 User’s Manual DRAM Sync. with System Clock Reprogram DRAM Controller, Chip-Selects I/O Port (CSCx,CSDx),...
Page 121: Data Retention Sequence
7.2.8 Data Retention Sequence Data is retained in the following sequence: 1. The external RESET signal is sent to the MC68VZ328. 2. The internal RESET signal is generated by synchronizing the external RESET signal with the CLK32 signal. 3. When the internal RESET is asserted, the DRAM controller will stop the current refresh operation and enter burst refresh mode, which is a consecutive CAS-before-RAS refresh cycle.
Page 122: Programming Model
COL8 Column Address MD8—This bit selects the column Bit 5 address bit for multiplexed address MD8. 7-12 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFFC00 Setting 00 = PA10 01 = PA21 10 = PA23 11 = Not valid 00 = PA11...
Page 123 Table 7-6. DRAM Memory Configuration Register Description (Continued) Name Refresh Cycle—This value determines the refresh rate for Bits 4–0 the DRAM controller. The refresh rate can be calculated using the equation shown in Example 7-1. The REF value is the time of 1 refresh cycle. Example 7-1.
Page 124: Dram Control Register
Bits BC1–0 are ignored. 00 = 256 01 = 512 10 = 1,024 11 = 2,048 These bits are reserved and should be set to 0. 0 = Normal address multiplexing. 1 = Slower address multiplexing. MC68VZ328 User’s Manual 0x(FF)FFFC02 BIT 0 Setting...
Page 125 Table 7-7. DRAM Control Register Description (Continued) Name Description Light Sleep—Setting this bit enables the core or Bit 4 LCD controller to access the DRAM when the RM bit is set (DRAM is in self-refresh mode). Self-refresh mode is temporarily interrupted for the DRAM access and automatically returns to self-refresh mode once the transfer is complete.
Page 126: Sdram Control Register
1 = PA0 (normally for 8-bit SDRAM). 00 = PA20. 01 = PA22. 10 = PA24. 11 = Force this bank address line to 0. See Table 7-9 on page 7-17 for program- ming examples. MC68VZ328 User’s Manual 0x(FF)FFFC04 BIT 0 BNKADDH BNKADDL RACL Setting...
Page 127: Table 7-9 Sdram Bank Address Programming Examples
Table 7-8. SDRAM Control Register Description (Continued) Name Description BNKADDL SDRAM Low Order Bank Address Line Bits 3–2 Selection—A 2-bit bank register selection address is generated by selecting the appropriate CPU address line. This register bit allows selection of the low order bit.
Page 128: Sdram Power-Down Register
7.3.4 SDRAM Power-down Register This register controls how the SDRAM and the MC68VZ328 operate during a power-down operation. The bit position and values are shown in the following register display. The details about the register settings are described in Table 7-10.
Page 129: Lcd Controller
Chapter 8 LCD Controller This chapter describes the operation of the liquid crystal display (LCD) controller and supplies the programming information necessary to implement it in design projects. The LCD controller provides display data for external LCD drivers or for an LCD panel. The LCD controller fetches display data directly from system memory through periodic DMA transfer cycles.
Page 130: Lcd Controller Operation
LCD gray palette mapping register (LGPMR). DMACLK Pixel Clock Interface Registers Control Logic Screen Line Buffer MC68VZ328 User’s Manual LCD Controller Interface Driver Frame Rate Control Cursor Logic LCD Bias Voltage Control...
Page 131: Connecting The Lcd Controller To An Lcd Panel
The LCD interface logic is used to pack the display data into the correct size and output it to the LCD panel’s data bus. The polarity of the LFLM, LP, and LCLK signals and pixel data can all be programmed to suit different LCD panel requirements.
Page 132: Controlling The Display
[39,0] [41,0] 1- bit LCD data bus (PBSIZ = 00) [1,0] [2,0] [19,0] [20,0] × 240 pixels in gray level display. A screen size larger than MC68VZ328 User’s Manual LINE n LINE 1 [m-8,0] [m-4,0] [m-7,0] [m-3,0] [m-6,0] [m-2,0] [m-5,0]...
Page 133: Format Of The Cursor
LCD Controller Operation Virtual Page Width Screen Starting Address Screen Width Cursor X Position Cursor Width Figure 8-3. LCD Screen Format The LCD screen width (LXMAX) and LCD screen height (LYMAX) registers are where the size of the LCD panel is specified. The LCD controller will start scanning the display memory at the location pointed to by the LCD screen starting address (LSSA) register.
Page 134: Mapping The Display Data
Table 8-1 on page 8-7. Use the LGPMR registers to program the grayscale level. LCD Drivers (1,0) (2,0) (1,Y-1) (2,Y-1) 1-bit-per-pixel mode (2,0) (3,0) (4,0) (X-6,Y-1) (X-5,Y-1) (X-4,Y-1) 2-bits-per-pixel mode (1,0) (2,0) (X-3,Y-1) (X-2,Y-1) MC68VZ328 User’s Manual (X-1,0) (X-1,Y-1) (5,0) (6,0) (7,0) (X-3,Y-1) (X-2,Y-1) (X-1,Y-1) (3,0) (X-1,Y-1)
Page 135: Table 8-1 Grey Palette Density
The Controlling Frame Rate Modulation function available in previous versions of the DragonBall integrated processor is not available in the MC68VZ328. Table 8-1. Grey Palette Density Density Density (in Decimal) 0.125...
Page 136: Using Low-Power Mode
Some panels may have a PANEL_OFF signal, which is used to turn off the panel for low-power mode. In an MC68VZ328 system, this signal is not supported, but can be easily implemented using a parallel I/O pin. The software can be programmed to achieve PANEL_OFF by using parallel I/O in the following sequence: 1.
Page 137: Self-Refresh Mode
-------------- - --------------------- - 60 Hz 240 lines 69.4 s During the same period, the line buffer must be filled. The following T cycle will hold up the bus: 320 pixels ---------------------------------------------------------------------------------------------------- - 16.67 MHz 16-bit bus 4.8 s Thus, the percentage of host bus time taken up by the LCD controller’s DMA is P 4.8‘...
Page 138: Programming Model
(A[19:00]). In other words, A[31:20] has a fixed value for a picture’s image. Reserved Reserved Bit 0 8-10 0x0000 0x0000 Description – 1—This field is the screen starting address MC68VZ328 User’s Manual 0x(FF)FFFA00 Setting See description. This bit is reserved and should be set to 0.
Page 139: Lcd Virtual Page Width Register
8.3.2 LCD Virtual Page Width Register The LCD virtual page width (LVPW) register contains the width of the displayed image. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-3.
Page 140: Lcd Screen Height Register
Reserved Reserved Bits 13–10 8-12 LCD Screen Height Register 0x01FF Description 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFFA0A BIT 0 Setting These bits are reserved and should be set to 0. See description. 0x(FF)FFFA18 BIT 0 CXP0 Setting 00 = Transparent, cursor is disabled.
Page 141: Lcd Cursor Y Position Register
Table 8-6. LCD Cursor X Position Register Description (Continued) Name CXPx Cursor X Position 9–0—These bits represent the cursor’s Bits 9–0 horizontal starting position, X, in terms of pixel count (from 0 to XMAX). 8.3.6 LCD Cursor Y Position Register The LCD cursor Y position (LCYP) register is used to determine the vertical pixel position of the cursor on the LCD panel.
Page 142: Lcd Cursor Width And Height Register
The settings for the bits in the register are listed in Table 8-9 on page 8-15. 8-14 0x0101 Description MC68VZ328 User’s Manual 0x(FF)FFFA1C Setting These bits are reserved and should be set to 0.
Page 143: Lcd Panel Interface Configuration Register
LBLKC BIT 7 BKEN TYPE RESET Table 8-9. LCD Blink Control Register Description Name BKEN Blink Enable—This bit determines if the cursor will blink or remain Bit 7 steady. Blink Divisor 6–0—These bits determine if the cursor will toggle Bits 6–0 once per a specified number of internal frame pulses plus one.
Page 144: Lcd Polarity Configuration Register
The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-12 on page 8-17. 8-16 LCKPOL 0x00 Description MC68VZ328 User’s Manual 0x(FF)FFFA21 BIT 0 FLMPOL LPPOL PIXPOL...
Page 145: Lcd Pixel Clock Divider Register
LACDRC BIT 7 ACDSLT ACD6 TYPE RESET Table 8-12. LACD Rate Control Register Description Name ACDSLT Clock Source Select—This bit selects the clock source for the Bit 7 internal counter that generates an LACD signal. ACDx Alternate Crystal Direction Control 6–0—These bits represent Bits 6–0 the ACD toggle rate control code.
Page 146: Lcd Clocking Control Register
Name Reserved Reserved Bits 15–10 8-18 Unused 0x00 Description 0x00FF Description MC68VZ328 User’s Manual 0x(FF)FFFA27 BIT 0 Setting 0 = Disable the LCD controller 1 = Enable the LCD controller See description The bit assignments for the 0x(FF)FFFA28 BIT 0...
Page 147: Lcd Panning Offset Register
LCD Frame Rate Control Modulation Register This register of address space 0x(FF)FFFA31 is used for frame rate modulation control in the MC68EZ328, but it is unused in the MC68VZ328. This register is removed and not available for the temporary storage of data.
Page 148: Lcd Gray Palette Mapping Register
PWM counter. The PWM output frequency is equal to the fre- quency of the input clock divided by 256. 8-20 0x84 Description CCPE SRC1–0 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFFA33 BIT 0 Setting See description See description 0x(FF)FFFA36 Setting These bits are reserved and should be set to 0.
Page 149: Refresh Mode Control Register
Table 8-18. PWM Contrast Control Register Description (Continued) Name CCPEN Contrast Control Enable—This bit is used to enable or dis- Bit 8 able the contrast control function. Pulse Width 7–0—This bit controls the pulse-width of the Bits 7–0 built-in pulse-width modulator, which controls the contrast of the LCD screen.
Page 150: Dma Control Register
;LCD panel data bus is 4 bits,4 level gray ;pixel clock rate equal 1/4 of LCDCLK from PLL ;refresh rate adjustment ;shift picture by 3 pixels ;switch on LCDC, 2 wait state for memory cycle MC68VZ328 User’s Manual 0x(FF)FFFA39 BIT 0 DMATM[2:0] Setting See description and table footnote.
Page 151: Interrupt Controller
This chapter describes the interrupt controller and all of the signals associated with it. The interrupt controller of the MC68VZ328 supports all internal interrupts as well as external edge- and level-sensitive interrupts. There are seven interrupt levels. Level 7 has the highest priority and level 1 has the lowest.
Page 152: Interrupt Processing
On the MC68VZ328, steps 2 and 4 operate exactly as they would on other M68000 devices, which are described in the M68000 User’s Manual. In step 2, the CPU’s status register (SR) is available to mask interrupts globally to determine which priority levels can currently generate interrupts.
Page 153: Exception Vectors
Each exception has a vector number and an exception vector, as described in Table 9-1. User interrupts are part of the exception processing on the MC68VZ328, and the vector numbers for user interrupts are configurable. For additional information regarding exception processing, see the M68000 Family Programmer’s Reference Manual.
Page 154: Reset
2.Reset vector 0 requires four words, unlike the other vectors which only require two words, and it is located in the supervisor program space. 3.Vector numbers 12–14, 16–23, and 48–63 are reserved for future enhancements by Motorola. No peripheral devices should be assigned to these numbers.
Page 155: Operation Mode Selection During Reset
CPU, and the RESET pin will not go low when this instruction is issued because it is an input-only signal. The MC68VZ328’s RESET signal should be held low for at least 1.2 s after V Section 4.3.2.1, “PLLCLK Initial Power-up Sequence,” on page 4-5 for detailed information about selecting the optimum RESET delay.
Page 156: Interrupt Vectors
9.4.2 Interrupt Vectors The MC68VZ328 provides one interrupt vector for each of the seven user interrupt levels. These interrupt vectors form the user interrupt vector section of Table 9-1 on page 9-3. The user interrupt vectors can be located anywhere within the 0x100 to 0x400 address range. The 5 most significant bits of the interrupt vector number are programmable, but the lower 3 bits reflect the interrupt level being serviced.
Page 157: Table 9-3 Interrupt Vector Register Description
5 bits to form an 8-bit vector number. The CPU uses the vector number to generate a vector address. During system startup, this register should be configured so that the MC68VZ328’s external and internal interrupts can be handled properly by their software handlers. If an interrupt occurs before the IVR has been programmed, the interrupt vector number 0x0F is returned to the CPU as an uninitialized interrupt, which has the interrupt vector 0x3C.
Page 158: Interrupt Control Register
IRQ1 is a level-sensitive interrupt. In this case, the external source of the interrupt must be cleared. Interrupt Control Register POL6 POL5 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFF302 BIT 0 Setting 0 = Negative polarity. 1 = Positive polarity.
Page 159 Table 9-4. Interrupt Control Register Description (Continued) Name IRQ2 Edge Trigger Select—When this bit is set, the IRQ2 signal is an Bit 10 edge-triggered interrupt. In edge-triggered mode, a 1 must be written to the IRQ2 bit in the interrupt status register to clear this interrupt. When this bit is low, IRQ2 is a level-sensitive interrupt.
Page 160: Interrupt Mask Register
It is set to 1 after reset. 9-10 Interrupt Mask Register 0x00FF 0xFFFF Description MC68VZ328 User’s Manual 0x(FF)FFF304 Settings These bits are reserved and should be set to 0. 0 = Enable EMUIRQ interrupt 1 = Mask EMUIRQ interrupt 0 = Enable real-time interrupt timer interrupt.
Page 161 Table 9-5. Interrupt Mask Register Description (Continued) Name MIRQ2 Mask IRQ2 Interrupt—When set, this bit indicates that IRQ2 Bit 17 is masked. It is set to 1 after reset. MIRQ1 Mask IRQ1 Interrupt—When set, this bit indicates that IRQ1 Bit 16 is masked.
Page 162: Interrupt Status Register
Emulation Module Status Register,” on page 16-10 for more infor- mation. 9-12 Interrupt Status Register 0x00000000 0x00000000 Description MC68VZ328 User’s Manual 0xFFFFF30C Settings These bits are reserved and should be set to 0. 0 = No emulator interrupt is pending.
Page 163 Table 9-6. Interrupt Status Register Description (Continued) Name Real-Time Interrupt Status (Real-Time Clock)—When set, this bit Bit 22 indicates that the real-time timer has reached its predefined fre- quency count. The frequency can be selected inside the real-time clock module, which can function as an additional timer. SPI1 SPI 1 Interrupt Status—When set, this bit indicates an interrupt Bit 21...
Page 164 Watchdog Timer Interrupt Request—This bit indicates that a Bit 3 watchdog timer interrupt is pending. This is a level 4 interrupt. 9-14 Description MC68VZ328 User’s Manual Settings 0 = No UART 2 interrupt request is pending. 1 = UART 2 interrupt request is pending.
Page 165 Table 9-6. Interrupt Status Register Description (Continued) Name UART1 UART 1 Interrupt Request—When set, this bit indicates that the Bit 2 UART 1 module needs service. This is a level 4 interrupt. TMR1 Timer 1 Interrupt Status—This bit indicates that a timer 1 event has Bit 1 occurred.
Page 166: Interrupt Pending Register
Bit 21 event from SPI unit 1. 9-16 Interrupt Pending Register 0x00000000 0x00000000 Description MC68VZ328 User’s Manual 0x(FF)FFF310 Settings These bits are reserved and should be set to 0. 0 = No emulator interrupt is pending. 1 = An emulator interrupt is pending.
Page 167 Table 9-7. Interrupt Pending Register Description (Continued) Name IRQ5 Interrupt Request Level 5—This bit, when set, indicates that an Bit 20 external device is requesting an interrupt on level 5. If the IRQ5 sig- nal is set to be a level-sensitive interrupt, the source of the interrupt must first be cleared.
Page 168 SPI2 SPI Unit 2 Interrupt Pending—When set, this bit indicates an inter- Bit 0 rupt event from SPI unit 2. 9-18 Description MC68VZ328 User’s Manual Settings 0 = No INT2 interrupt is pending. 1 = An INT2 interrupt is pending.
Page 169: Interrupt Level Register
9.6.6 Interrupt Level Register TIMER 2, UART 2, PWM 2, and SPI 1 are new modules to the MC68VZ328 compared to the previous version, MC68EZ328. Interrupts generated from these modules are level configurable. The interrupt level control register (ILCR) controls the interrupt level for these interrupts.
Page 170: Keyboard Interrupts
ORed together and generate an interrupt that indicates to the core that a key has been pressed. Pen Interrupts The MC68VZ328 is designed to support pen and touch panel inputs. In most of these systems, the setup involves a touch panel connected to an analog-to-digital (A/D) converter and the microprocessor. To achieve low power consumption and system performance, the A/D is usually connected to an interrupt of the microprocessor.
Page 171: Port Configuration
I/O function. Some pins have multiple dedicated functions assigned to them. Selection of these functions is controlled by other registers in the MC68VZ328. Port D is unique in that it is used for handling external interrupts. It has four dedicated interrupt control registers in addition to the previously referenced four registers.
Page 172: Status Of I/O Ports During Reset
Status of I/O Ports During Reset Two types of resets affect the states of the MC68VZ328’s I/O ports: warm reset and power-up reset. A warm reset refers to any reset initiated while power to the processor remains uninterrupted. A power-up reset occurs the first time power is supplied to the MC68VZ328.
Page 173: Power-Up Reset
System Clock (SYSCLK) 32 kHz Clock External Reset (Hardware Reset) Internal Reset Internal Reset Pulse Ports A, C, D, E, F, G, J, & K Ports B & M Figure 10-1. I/O Port Warm Reset Timing As shown in Figure 10-1, resets for Ports A, C–G, J, and K are triggered by the assertion of the internal reset signal.
Page 174: Summary Of Port Behavior During Reset
The following subsections describe details of the I/O ports’ operation. 10.3.1 Data Flow from the I/O Module The operation of a port connected to another module in the MC68VZ328 is illustrated in Figure 10-2 on page 10-5. 10-4 Warm Reset MC68VZ328 User’s Manual...
Page 175: Data Flow To The I/O Module
“data from module” line is connected to the serial peripheral interface module’s TXD signal (SPITXD). Because SPITXD is output-only, the MC68VZ328 asserts the “output enable from module” line, thus enabling the output and disabling the “data to module” line. As long as the SELx bit of the port’s select register is clear (the default is set at reset), the SPI module pin function is enabled.
Page 176: Port Pull-Up And Pull-Down Resistors
Port A functions either as a GPIO (PA[7:0]) or the lower data byte of the data bus (D[7:0]). Port A can be used as PA[7:0] only when the MC68VZ328 is operating as an 8-bit system by setting the WDTH8 bit in the system control register (0xFFFFF000).
Page 177: Port A Direction Register
10.4.1.1 Port A Direction Register The Port A direction register controls the direction (input or output) of the line associated with the PADATA bit position. The settings for the bit positions are shown in Table 10-4. PADIR BIT 7 DIR7 DIR6 TYPE RESET...
Page 178: Port A Pull-Up Enable Register
PBDATA bit position. When the data bit is assigned to a dedicated I/O function, the direction bits are ignored. The settings for the bit positions are shown in Table 10-7 on page 10-9. 10-8 0xFF 0 = Pull-up resistors are disabled 1 = Pull-up resistors are enabled MC68VZ328 User’s Manual 0x(FF)FFF402 BIT 0 Setting...
Page 179: Port B Data Register
PBDIR BIT 7 DIR7 DIR6 TYPE RESET Table 10-7. Port B Direction Register Description Name DIRx Direction—These bits control the direction of the pins. They reset Bits 7–0 to 0. With the exception of bit 6, if a bit is selected as a dedicated I/O in PBSEL, the DIR bit is ignored 10.4.2.2 Port B Data Register...
Page 180: Port B Dedicated I/O Functions
GPIO Function Dedicated I/O Functions Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 MC68VZ328 User’s Manual CSB0 CSB1/SDWE CSC0/RAS0 CSC1/RAS1 CSD0/CAS0 CSD1/CAS1 TIN/TOUT PWMO1...
Page 181: Port B Select Register
PBPUEN Port B Pull-up Enable Register BIT 7 TYPE RESET Table 10-10. Port B Pull-up Enable Register Description Name Description Pull-up—These bits enable the pull-up resis- Bits 7–0 tors on the port. 10.4.2.5 Port B Select Register The Port B select register (PBSEL) determines if a bit position in the data register (PBDATA) is assigned as a general purpose I/O or to a dedicated I/O function.
Page 182: Port C Direction Register
DIRx is set to 0 1 = Drives the output signal high when DIRx is set to 1 or the external signal is high when DIRx is set to 0 MC68VZ328 User’s Manual 0x(FF)FFF410 BIT 0...
Page 183: Port C Dedicated I/O Functions
accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as an output. The actual value on the pin is reported when these bits are read, regardless of whether they are configured as input or output. 10.4.3.3 Port C Dedicated I/O Functions The eight PCDATA lines are multiplexed with the LCD controller dedicated I/O signals whose...
Page 184: Port C Select Register
I/O port signals are connected to the pins. 10-14 Port C Select Register SEL6 SEL5 SEL4 SEL3 0xFF 0 = The dedicated function pins are 1 = The I/O port function pins are connected. MC68VZ328 User’s Manual 0x(FF)FFF413 BIT 0 SEL2 SEL1 SEL0 Setting connected.
Page 185: Port D Operation
Port D generates nine interrupt signals. Eight of these interrupts are generated by the bits of each port. One bit is the logical OR result of all eight bits, which is applied to the MC68VZ328 interrupt controller as a level 4 keyboard interrupt (KB) in the interrupt status register. See Section 9.6.4, “Interrupt Status Register,”...
Page 186: Port D Registers
Direction—These bits control the direction of the pins in an 8-bit sys- Bits 7–0 tem. They reset to 0. 10-16 Port D Direction Register DIR5 DIR4 DIR3 0x00 Description MC68VZ328 User’s Manual 0x(FF)FFF418 BIT 0 DIR2 DIR1 DIR0 Setting 0 = Input 1 = Output...
Page 187: Port D Data Register
10.4.5.2 Port D Data Register The settings for the PDDATA bit positions are shown in Table 10-18. PDDATA BIT 7 TYPE RESET Table 10-18. Port D Data Register Description Name Description Data—These bits reflect the Bits 7–0 status of the I/O signal. The eight PDDATA lines are multiplexed with the INT and IRQ dedicated I/O signals whose assignments are shown in Table 10-19.
Page 188: Port D Interrupt Options
Table 10-20. Port D Pull-up Enable Register Description Name Pull-up—These bits enable the pull-up resistors on the port. Bits 7–0 10-18 NOTE: 0xFF Description MC68VZ328 User’s Manual 0x(FF)FFF41A BIT 0 Setting 0 = Pull-up resistors are disabled 1 = Pull-up resistors are enabled...
Page 189: Port D Select Register
10.4.5.5 Port D Select Register The Port D select register (PDSEL) determines if a bit position in the Port D data register (PDDATA) is assigned as a GPIO or to a dedicated I/O function. The settings for the bit positions of PDSEL are shown in Table 10-21.
Page 190: Port D Interrupt Request Enable Register
0 = Interrupt disabled. 1 = Interrupt enabled. KBEN5 KBEN4 KBEN3 0x00 Description 0 = The keyboard interrupt is disabled. 1 = The keyboard interrupt is enabled. MC68VZ328 User’s Manual 0x(FF)FFF41D BIT 0 IQEN2 IQEN1 IQEN0 Setting 0x(FF)FFF41E BIT 0...
Page 191: Port E Registers
PDIRQEG Port D Interrupt Request Edge Register BIT 7 TYPE RESET Table 10-25. Port D Interrupt Request Edge Register Description Name Description Reserved Reserved Bits 7–4 IQEGx Edge Enable—The polarity of the rising or Bits 3–0 falling edge is selected by the POLx bits. 10.4.6 Port E Registers Port E is composed of the following 8-bit general-purpose I/O registers:...
Page 192: Port E Dedicated I/O Functions
DIRx is set to 0 GPIO Function Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 MC68VZ328 User’s Manual 0x(FF)FFF421 BIT 0 Setting Dedicated I/O Function SPITXD SPIRXD SPICLK2...
Page 193: Port E Pull-Up Enable Register
Table 10-28. Port E Dedicated Function Assignments (Continued) 10.4.6.4 Port E Pull-up Enable Register The Port E pull-up enable register (PEPUEN) controls the pull-up resistors for each line in Port E. The settings for the bit positions of the PEPUEN register are shown in Table 10-29. PEPUEN Port E Pull-up Enable Register BIT 7...
Page 194: Port F Registers
Direction—These bits control the direction of the pins in an 8-bit Bits 7–0 system. They reset to 0. 10-24 Port F Direction Register DIR5 DIR4 DIR3 0x00 Description MC68VZ328 User’s Manual 0x(FF)FFF428 BIT 0 DIR2 DIR1 DIR0 Setting 0 = Input 1 = Output...
Page 195: Port F Data Register
10.4.7.2 Port F Data Register The settings for the bit positions of the PFDATA register are shown in Table 10-32. PFDATA BIT 7 TYPE RESET Table 10-32. Port F Data Register Description Name Description Data—These bits reflect the Bits 7–0 status of the I/O signal in an 8-bit system.
Page 196: Port F Dedicated I/O Functions
Bit 7 is used for the chip-select signal CSA1. See Section 6.2, “Chip-Select Operation,” on page 6-2 for detailed information. 10-26 GPIO Function Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 MC68VZ328 User’s Manual Dedicated I/O Function LCONTRAST IRQ5 CLKO CSA1...
Page 197: Port F Pull-Up/Pull-Down Enable Register
10.4.7.4 Port F Pull-up/Pull-down Enable Register The Port F pull-up/pull-down enable register (PFPUEN) controls the pull-up resistors for each line in Port F. The settings for the PFPUEN bit positions are shown in Table 10-34. PFPUEN Port F Pull-up/Pull-down Enable Register BIT 7 TYPE RESET...
Page 198: Port G Registers
The settings for the bit positions of the PGDATA register are shown in Table 10-37 on page 10-29. 10-28 Port G Direction Register DIR5 DIR4 DIR3 0x00 These bits are reserved and should be set to 0 = Input 1 = Output MC68VZ328 User’s Manual 0x(FF)FFF430 BIT 0 DIR2 DIR1 DIR0 Setting...
Page 199: Port G Dedicated I/O Functions
PGDATA BIT 7 TYPE RESET Table 10-37. Port G Data Register Description Name Description Reserved Reserved Bits 7–6 Data—These bits reflect the Bits 5–0 status of the I/O signal in an 8-bit system. Port G is multiplexed with address line A0 and several dedicated I/O functions. These pins can be programmed as GPIO when the address bus and the dedicated I/O signals are not in use.
Page 200: Port G Operational Considerations
BUSW is the default bus width for the CSA0 signal. The DTACK signal is the external input data acknowledge signal. The MC68VZ328 microprocessor will latch the BUSW signal at the rising edge of the Reset signal. Its mode will determine the default bus width for CSA0. Bit 1 is Address 0. After system reset, this signal defaults to A0.
Page 201: Port J Registers
PGSEL BIT 7 TYPE RESET Table 10-40. Port G Select Register Description Name Description Reserved Reserved Bits 7–6 SELx Select—These bits select whether the internal chip Bits 5–0 function or I/O port signals are connected to the pins. 10.4.9 Port J Registers Port J is composed of the following four general-purpose I/O registers: •...
Page 202: Port J Data Register
DIRx is set to 0 GPIO Function Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 MC68VZ328 User’s Manual 0x(FF)FFF439 BIT 0 Setting Dedicated I/O Function MOSI MISO SPICLK1 RXD2...
Page 203: Port J Pull-Up Enable Register
Table 10-43. Port J Dedicated I/O Function Assignments (Continued) Bits 0–3 are control signals connected to SPI 1. Their operation is detailed in Section 13.2.4, “SPI 1 Signals,” on page 13-3. The remaining 4 bits are control signals for UART 2; more information appears in Section 14.2.3, “Serial Interface Signals,”...
Page 204: Port K Registers
The settings for the PKDATA register bit positions are shown in Table 10-47 on page 10-35. 10-34 Port K Direction Register DIR5 DIR4 DIR3 0x00 0 = The pins are inputs. 1 = The pins are outputs. MC68VZ328 User’s Manual 0x(FF)FFF440 BIT 0 DIR2 DIR1 DIR0 Setting...
Page 205: Port K Dedicated I/O Functions
PKDATA BIT 7 TYPE RESET Table 10-47. Port K Data Register Description Name Description Data—These bits reflect the status of Bits 7–0 the I/O signal in an 8-bit system. Port K is multiplexed with the IrDA, SPI, and LCD controller signals. These pins can be programmed as GPIO when the dedicated I/O signals are not in use.
Page 206: Port K Pull-Up/Pull-Down Enable Register
1 = Pull-up and pull-down resistors are enabled Port K Select Register SEL6 SEL5 SEL4 SEL3 0xFF 0 = The dedicated function pins are connected. 1 = The I/O port function pins are connected. MC68VZ328 User’s Manual 0x(FF)FFF442 BIT 0 Setting 0x(FF)FFF443 BIT 0 SEL2 SEL1 SEL0...
Page 207: Port M Registers
10.4.11 Port M Registers Port M is composed of the following four general-purpose I/O registers: • Port M direction register (PMDIR) • Port M data register (PMDATA) • Port M pull-up enable register (PMPUEN) • Port M select register (PMSEL) Each signal in the PMDATA register connects to an external pin.
Page 208: Port M Data Register
DIRx is set to 0 1 = Drives the output signal high when DIRx is set to 1 or the external signal is high when DIRx is set to 0 MC68VZ328 User’s Manual 0x(FF)FFF449 BIT 0...
Page 209: Port M Dedicated I/O Functions
10.4.11.3 Port M Dedicated I/O Functions The six PMDATA lines are multiplexed with the dedicated I/O signals whose assignments are shown in Table 10-53. Table 10-53. Port M Dedicated I/O Function Assignments All of the dedicated I/O functions are involved in the operation of the DRAM controller. See Chapter 7, “DRAM Controller,”...
Page 210: Port M Select Register
SEL5 SEL4 SEL3 0x3F These bits are reserved and should be set to 0 = The dedicated function pins are connected. 1 = The I/O port function pins are connected. MC68VZ328 User’s Manual 0x(FF)FFF44B BIT 0 SEL2 SEL1 SEL0 Setting...
Page 211: Real-Time Clock
4 interrupts to the interrupt controller. The RTC can also generate a watchdog system reset. The following sections describe how each block operates and interacts with other modules in both the RTC and the MC68VZ328. TOD Clock...
Page 212: Rtc Overview
CLK32; see Section 4.5, “Introduction to the Power Control Module,” on page 4-10 for detailed information on the power modes of the MC68VZ328. The actual frequency of the CLK32 is determined by the external crystal used as the crystal oscillator. The MC68VZ328 supports either a 32.768 kHz or a 38.4 kHz frequency crystal.
Page 213: Time-Of-Day Counter
To allow maximum flexibility in design, each of the four counters in the TOD clock can accept values that exceed their valid range. The MC68VZ328 does not check for range validity. If an out-of-range value is entered, the counter will reset to zero the next time it is incremented. For example, if 26 is written to the hours counter, the counter will remain 26 until incremented by the minutes counters.
Page 214: Watchdog Timer
(RTCIENR) enable each of the eight different predefined rates. When the real-time interrupt occurs, it applies a level 4 interrupt to the MC68VZ328 interrupt controller. The real-time clock (RTCEN bit in the RTCCTL) or the watchdog timer (EN bit in the watchdog register) must be enabled for the real-time interrupt timer to operate.
Page 215: Rtc Time Register
11.2 Programming Model Section 11.2.1, “RTC Time Register,” through Section 11.2.9, “Stopwatch Minutes Register,” provide programming information on the real-time clock. 11.2.1 RTC Time Register The real-time clock hours, minutes, and seconds (RTCTIME) register is used to program the hours, minutes, and seconds.
Page 216: Rtc Day Count Register
Days—This field indicates the current setting Bits 8–0 of the day. 11-6 RTC Day Counter Register 0x0XXX Description These bits are reserved and should be set to The bits can be set to any value between 0 and 511. MC68VZ328 User’s Manual 0x(ff)FFFB1A DAYS Setting...
Page 217: Rtc Alarm Register
11.2.3 RTC Alarm Register The real-time clock alarm (RTCALRM) register is used to configure the alarm. The hours, minutes, and seconds can be read or written at any time. After a write, the current time assumes the new values. The settings for the RTCTIME register are described in Table 11-4.
Page 218: Rtc Day Alarm Register
11-8 RTC Day Alarm Register 0x0000 Description These bits are reserved and should be set to 0. The bits can be set to any value between 0 and 511. MC68VZ328 User’s Manual 0x(ff)FFFB1C DAYSAL Setting...
Page 219: Watchdog Timer Register
11.2.5 Watchdog Timer Register The watchdog timer (WATCHDOG) register provides all of the control of the watchdog timer. It provides bits to enable the watchdog timer and to determine if the result of a time out is an interrupt or a system reset.
Page 220: Rtc Control Register
This bit is reserved and should be set to 0. 0 = Reference frequency is 32.768 kHz 1 = Reference frequency is 38.4 kHz. These bits are reserved and should be set to MC68VZ328 User’s Manual 0x(ff)FFFB0C REFREQ Setting (default).
Page 221: Table 11-8 Rtc Interrupt Status Register Description
RTCISR RTC Interrupt Status Register RIS7 RIS6 RIS5 RIS4 TYPE RESET Table 11-8. RTC Interrupt Status Register Description Name Description RIS7 Real-Time Interrupt Status Bit 7—This bit Bit 15 shows the status of real-time interrupt 7. RIS6 Real-Time Interrupt Status Bit 6—This bit Bit 14 shows the status of real-time interrupt 6.
Page 222: Rtc Interrupt Enable Register
32.768 kHz Reference Clock 1.9531 ms 3.9062 ms 7.8125 ms 15.625 ms 31.25 ms 62.5 ms 125 ms 250 ms MC68VZ328 User’s Manual Setting 38.4 kHz Reference Clock 600 Hz 1.6666 ms 300 Hz 3.3333 ms 150 Hz 6.6666 ms 75 Hz 13.3333 ms...
Page 223: Table 11-10 Rtc Interrupt Enable Register Description
RTCIENR RTC Interrupt Enable Register RIE7 RIE6 RIE5 RIE4 TYPE RESET Table 11-10. RTC Interrupt Enable Register Description Name RIE7 Real-Time Interrupt Enable Bit 7—This bit enables the Bit 15 real-time interrupt 7. The frequency of this interrupt is shown in Table 11-9 on page 11-12. RIE6 Real-Time Interrupt Enable Bit 6—This bit enables the Bit 14...
Page 224: Stopwatch Minutes Register
The highest possible value is 62 minutes. The countdown will not be activated again until a non- zero value, which is less than 63 minutes, is written to this register. MC68VZ328 User’s Manual Setting 0 = Alarm interrupt is disabled. 1 = Alarm interrupt is enabled.
Page 225: General-Purpose Timers
Chapter 12 General-Purpose Timers This chapter describes in detail the operation of the general-purpose timer modules of the MC68VZ328. The GP timers consist of two general-purpose 16-bit timers, a prescaler, and compare and capture registers. Each timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse.
Page 226: Clock Source And Prescaler
436 seconds using a 38.4 kHz oscillator. Of the four clock sources, only CLK32 continues to operate while the MC68VZ328 is in sleep mode. See Section 4.5.2, “CGM Operation During Sleep Mode,” on page 4-12 for more information on CLK32 operation during sleep mode.
Page 227: Timer Capture Register
When a capture event occurs, the CAPT status bit is set in the TSTATx register. A TIMERx interrupt is sent to the MC68VZ328 interrupt controller if the capture function is enabled and the IRQEN bit of the TCTLx register is set. The timer is disabled at reset.
Page 228: Cascaded Timers
When the MSW status bit sets, check the status bit of the LSW. If it is not set, loop until it does set. 12-4 TIN To Timer 1 Timer 2 Timer 2 Timer 2 Timer 1 Timer 1 MC68VZ328 User’s Manual TOUT From Timer 1 Timer 2...
Page 229: Figure 12-2 Compare Routine For 32-Bit Cascaded Timers
GP Timer Overview Wait on MSW MSW status bit set? LSW status bit set? Set flag 32-bit compare Figure 12-2. Compare Routine for 32-Bit Cascaded Timers General-Purpose Timers 12-5...
Page 230: Programming Model
12-6 Timer Control Register 1 0x0000 Timer Control Register 2 0x0000 These bits are reserved and should be set to 0. 0 = Restart mode (default). 1 = Free-running mode. MC68VZ328 User’s Manual 0x(FF)FFF600 IRQEN CLKSOURCE 0x(FF)FFF610 IRQEN CLKSOURCE Setting...
Page 231 Table 12-2. Timer Control Register Description (Continued) Name Description Capture Edge—This field selects the type of Bits 7–6 transition on the TIN input that triggers a cap- ture event. Note: To use TIN/TOUT as a TIN input, ensure that the SEL6 bit in the Port B select register (PBSEL) is cleared.
Page 232: Timer Prescaler Registers 1 And 2
The value range of this field is between 1 and 256. 12-8 Timer Prescaler Register 1 0x0000 Timer Prescaler Register 2 0x0000 0x00 = Divide by 1 0xFF = Divide by 256 MC68VZ328 User’s Manual 0x(FF)FFF602 BIT 0 Prescaler 0x(FF)FFF612 BIT 0 Prescaler Setting —...
Page 233: Timer Compare Registers 1 And 2
12.2.3 Timer Compare Registers 1 and 2 Each timer compare (TCMPx) register contains the value that is compared with the counter. A compare event is generated when the counter matches the value in this register. This register is set to 0xFFFF at system reset.
Page 234: Timer Capture Registers 1 And 2
12-10 Timer Capture Register 1 CAPTURE 0x0000 Timer Capture Register 2 CAPTURE 0x0000 This field has a valid range 0x0000 to 0xFFFF. MC68VZ328 User’s Manual 0x(FF)FFF606 BIT 0 0x(FF)FFF616 BIT 0 Setting...
Page 235: Timer Counter Registers 1 And 2
12.2.5 Timer Counter Registers 1 and 2 Each read-only timer counter (TCNx) register contains the current count. The TCNx can be read at any time without affecting the current count. The settings for the registers are described in Table 12-6. TCN1 BIT 15 TYPE...
Page 236: Timer Status Registers 1 And 2
Not Used 0x0000 0 = No capture event occurred. 1 = A capture event has occurred. 0 = No compare event occurred. 1 = A compare event has occurred. MC68VZ328 User’s Manual 0x(FF)FFF60A BIT 0 CAPT COMP 0x(FF)FFF61A BIT 0...
Page 237: Serial Peripheral Interface 1 And 2
While SPI 2 operates as a master-mode-only SPI module, SPI 1 represents an enhanced version of the SPI 2 design. Equipped with a data FIFO, SPI 1 may operate as a master- or slave-configurable SPI interface module, allowing the MC68VZ328 to interface with either an external SPI master or an SPI slave device.
Page 238: Spi 1 Operation
Using SPI 1 as Master If SPI 1 is configured as master, it uses a serial link to transfer data between the MC68VZ328 and a peripheral device. A chip-enable signal and a clock signal are used to transfer data between the two devices.
Page 239: Spi 1 Phase And Polarity Configurations
13.2.3 SPI 1 Phase and Polarity Configurations When SPI 1 is used as master, the SPICLK1 signal is used to transfer data in and out of the shift register. Data is clocked using any one of four programmable clock phase and polarity variations. During phase 0 operation, output data changes on the falling clock edges, and input data is shifted in on rising edges.
Page 240: Spi 1 Programming Model
Bits 7–0 13-4 × 16 RxFIFO, which receives data from an external SPI DATA 0x0000 The data in this register has no meaning if the RR bit in the interrupt control/status register is cleared. MC68VZ328 User’s Manual 0x(FF)FFF700 BIT 0 Setting...
Page 241: Spi 1 Transmit Data Register
13.3.2 SPI 1 Transmit Data Register This write-only data register is the top of the 8 TxFIFO is not full, even if the XCH bit is set. For example, a user may write to TxFIFO during the SPI data exchange process. In either master or slave mode, a maximum of 8 data words are loaded. Data written to this register can be of either 8-bit or 16-bit size.
Page 242: Spi 1 Control/Status Register
0 = Serial peripheral interface is disabled 1 = Serial peripheral interface is enabled 1 = Initiates exchange (write) or busy (read) 0 = Idle 0 = Active low 1 = Active high MC68VZ328 User’s Manual 0x(FF)FFF704 BIT COUNT Setting...
Page 243 Table 13-3. SPI 1 Control/Status Register Description (Continued) Name Description SSCTL SS Waveform Select—In master mode, this Bit 6 bit selects the output wave form for the SS sig- nal. In slave mode, this bit controls RxFIFO advancement. Phase—This bit controls the clock/data phase Bit 5 relationship.
Page 244: Spi 1 Interrupt Control/Status Register
0 = Disable data ready interrupt enable. 1 = Enabled data ready interrupt enable. 0 = Disable TxFIFO full interrupt. 1 = Enable TxFIFO full interrupt. 0 = Disable TxFIFO half interrupt. 1 = Enable TxFIFO half interrupt. MC68VZ328 User’s Manual 0x(FF)FFF706 Setting...
Page 245 Table 13-4. SPI 1 Interrupt Control/Status Register Description (Continued) Name Description TEEN TxFIFO Empty Interrupt Enable—This bit, Bit 8 when set, causes an interrupt to be generated when the TxFIFO buffer is empty and the TE bit is set. Bit Count Overflow—This bit is set when the Bit 7 SPI is in “slave SPI FIFO advanced by SS rising edge”...
Page 246: Spi 1 Test Register
The settings for this register are described in Table 13-6 on page 13-11. 13-10 SPI 1 Test Register SSTATUS RXCNT 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFF708 TXCNT Setting These bits are reserved and should be set to 0. See description. 0000 = RXFIFO is empty.
Page 247: Spi 2 Overview
It provides the clock for data transfer and can only function as a master device. It is fully compatible with the serial peripheral interface on Motorola’s 68HC05 and 68HC11 microprocessors. Figure 13-3 shows the SPI 2 block diagram.
Page 248: Spi 2 Operation
The serial peripheral interface 2 operates as a master-mode-only SPI module using a serial link to transfer data between the MC68VZ328 and a peripheral device. A chip-enable signal and a clock signal are used to transfer data between the two devices. If the external device is a transmit-only device, SPI 2’s output port is freed to be used for other purposes.
Page 249: Spi 2 Phase And Polarity Configurations
13.5.1 SPI 2 Phase and Polarity Configurations The SPI 2 module uses the SPICLK2 signal to transfer data in and out of the shift register. Data is clocked using any one of four programmable clock phase and polarity variations. In phase 0 operation, output data changes on the falling clock edges and input data is shifted in on rising edges.
Page 250: Spi 2 Programming Model
XCH bit is set. This field contains unknown data if it is read while the XCH bit is set. 13-14 SPI 2 Data Register DATA 0x0000 The data in this register has no meaning if the RR bit in the interrupt control/status register is clear. NOTE: MC68VZ328 User’s Manual 0x(FF)FFF800 Setting...
Page 251: Spi 2 Control/Status Register
13.6.3 SPI 2 Control/Status Register The SPI 2 control/status (SPICONT2) register controls how the SPI 2 module operates and reports its status. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 13-8. SPICONT2 SPI 2 Control/Status Register DATA RATE...
Page 252 1 = Phase 1 operation. 0 = Active high polarity (0 = idle). 1 = Active low polarity (1 = idle). 0000 = 1-bit transfer. 0001 = 2-bit transfer. 1110 = 15-bit transfer. 1111 = 16-bit transfer. MC68VZ328 User’s Manual Setting...
Page 253: Universal Asynchronous Receiver/Transmitter 1 And
This chapter describes both UARTs in the DragonBall VZ integrated processor. The two UART ports in the MC68VZ328 may be used to communicate with external serial devices. UART 1 in the DragonBall VZ processor is identical to the UART in the DragonBall EZ processor, while UART 2 represents an enhanced version of UART 1.
Page 254: Serial Operation
1 full bit. If parity is used, the parity bit is transmitted after the most significant bit. Figure 14-2 on page 14-3 illustrates a character in NRZ mode. 14-2 RxFIFO Receiver Serial Interface TxFIFO Transmitter MC68VZ328 User’s Manual RxD x Infrared Interface TxD x UCLK CTS x RTS x...
Page 255: Irda Mode
Figure 14-2. NRZ ASCII “A” Character with Odd Parity 14.2.2 IrDA Mode Infrared (IrDA) mode uses character frames as NRZ mode does, but, instead of driving ones and zeros for a full bit-time period, zeros are transmitted as three-sixteenth (or less) bit-time pulses, and ones remain low.
Page 256: Uart Operation
FIFO EMPTY interrupt should be enabled. The interrupt service routine should load data until the TX AVAIL bit in the UTX register is clear or until there is no more data to transmit. The transmitter does not generate another interrupt until the FIFO has completely emptied. 14-4 MC68VZ328 User’s Manual...
Page 257: Cts Signal Operation
If the driver software has excessive interrupt service latency time, use the FIFO HALF interrupt. With UART 1, the transmitter generates an interrupt when the FIFO has fewer than 4 bytes remaining. Because UART 2 has a larger FIFO buffer, the transmitter generates an interrupt when the FIFO has a number of empty slots that is less than or equal to the number specified by the TxFIFO level marker of the FIFO level marker interrupt register.
Page 258: Receiver Operation
The baud generator provides the bit clocks to the transmitter and receiver blocks. It consists of two prescalers, an integer prescaler, and a second non-integer prescaler, as well as a 2 page 14-7 illustrates a block diagram of the baud rate generator. 14-6 MC68VZ328 User’s Manual divider. Figure 14-4 on...
Page 259: Divider
PRE SEL Master Clock BAUD SRC SYSCLK UCLK IN PCLK (Divide by 2 CLK MODE CLK SRC Figure 14-4. Baud Rate Generator Block Diagram The baud rate generator’s master clock source can be the system clock (SYSCLK), or it can be provided by the UCLK pin (input mode).
Page 260: Table 14-1 Non-Integer Prescaler Values
Table 14-2. Non-Integer Prescaler Settings Mode IrDA 14-8 Minimum Divisor Maximum Divisor 3 127/128 7 63/64 15 31/32 31 15/16 63 7/8 127 3/4 255 1/2 — — Select (Binary) Step Value (Hex) MC68VZ328 User’s Manual Step Size 1/128 1/64 1/32 1/16 — 0x20...
Page 261: Integer Prescaler
14.3.3.3 Integer Prescaler The baud rate generator can provide standard baud rates from many system clock frequencies. Table 14-3 contains the values that should be used in the UBAUD register for a default 33.16 MHz system clock frequency. Table 14-3. Selected Baud Rate Settings Baud Rate 230400 115200...
Page 262: Programming Model
Bit 10 and checker. This bit has no function if the PEN bit is low. 14-10 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFF900 Setting 0 = UART 1 module is disabled 1 = UART 1 module is enabled 0 = Receiver is disabled and the...
Page 263 Table 14-4. UART 1 Status/Control Register Description (Continued) Name STOP Stop Bit Transmission—This bit controls the number of stop Bit 9 bits transmitted after a character. This bit has no effect on the receiver, which expects one or more stop bits. 8- or 7-Bit—This bit controls the character length.
Page 264: Uart 1 Baud Control Register
100 = Divide by 16. 101 = Divide by 32. 110 = Divide by 64. 111 = Divide by 128. These bits are reserved and should be set to See description. MC68VZ328 User’s Manual 0x(FF)FFF902 BIT 0 PRESCALER Setting system clock.
Page 265: Uart 1 Receiver Register
14.4.3 UART 1 Receiver Register The UART 1 receiver (URX1) register indicates the status of the receiver FIFO and character data. The FIFO status bits reflect the current status of the FIFO. At initial power up, these bits contain random data. Before enabling the receiver interrupts, the UEN and RXEN bits in the USTCNT register should be set.
Page 266: Uart 1 Transmitter Register
CTS1 BUSY BREAK CTS1 STAT 0x0000 Description MC68VZ328 User’s Manual Setting 0 = Character has no framing error 1 = Character has a framing error 0 = Character is not a break character 1 = Character is a break character...
Page 267 Table 14-7. UART 1 Transmitter Register Description (Continued) Name FIFO FIFO Half (FIFO Status)—This read-only bit indicates that the HALF transmitter FIFO is less than half full. This bit generates a Bit 14 maskable interrupt. Transmit FIFO Available (FIFO Status)—This read-only bit AVAIL indicates that the transmitter FIFO has at least one slot avail- Bit 13...
Page 268: Uart 1 Miscellaneous Register
Reserved Bits 9–8 14-16 BAUD RESET 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFF908 Setting 0 = Normal mode. 1 = Test mode. 0 = Bit clock is generated by the baud rate generator. 1 = Bit clock is supplied by the UCLK pin.
Page 269 Table 14-8. UART 1 Miscellaneous Register Description (Continued) Name RTS1 RTS1 Control—This bit selects the function of the RTS1 pin. CONT Bit 7 RTS1 Request to Send Pin—This bit controls the RTS1 pin when Bit 6 the RTS1 CONT bit is 0. IRDAEN Infrared Enable—This bit enables the IrDA interface.
Page 270: Uart 1 Non-Integer Prescaler Register
110 = Divide range is 128 to 255 1/2 in 1/2 steps. 111 = Disable the non-integer prescaler. 0000 0000. Step = 0. 0000 0001. Step = 1. 1111 1110. Step = 254. 1111 1111. Step = 255. MC68VZ328 User’s Manual 0x(FF)FFF90A BIT 0 STEP VALUE Setting...
Page 271: Non-Integer Prescaler Programming Example
14.4.7 Non-Integer Prescaler Programming Example The following steps show how to generate a 3.072 MHz clock frequency from a 16.580608 MHz clock source. 1. Calculate the divisor: divisor = 16.580608 MHz ÷ 3.072000 MHz = 5.397333 2. Find the value for the SELECT field in the NIPR. The divisor is between four and eight, so Table 14-1 on page 14-8 indicates that the SELECT field is 001.
Page 272: Uart 2 Status/Control Register
7-bit operation, the transmitter ignores data bit 7 and, when receiving, the receiver forces data bit 7 to 0. 14-20 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFF910 Setting 0 = UART 2 module is disabled 1 = UART 2 module is enabled...
Page 273 Table 14-10. UART 2 Status/Control Register Description (Continued) Name ODEN Old Data Enable—This bit enables an interrupt when the OLD Bit 7 DATA bit in the URX register is set. CTSD CTS2 Delta Enable—When this bit is high, it enables an inter- Bit 6 rupt when the CTS2 pin changes state.
Page 274: Uart 2 Baud Control Register
100 = Divide by 16. 101 = Divide by 32. 110 = Divide by 64. 111 = Divide by 128. These bits are reserved and should be set to 0. See description. MC68VZ328 User’s Manual 0x(FF)FFF912 BIT 0 PRESCALER Setting...
Page 275: Uart 2 Receiver Register
14.4.10 UART 2 Receiver Register The UART 2 receiver (URX2) register indicates the status of the receiver FIFO and character data. The FIFO status bits reflect the current status of the FIFO. At initial power up, these bits contain random data. Before the receiver interrupts are enabled, the UEN and RXEN bits in the USTCNT register should be set.
Page 276: Uart 2 Transmitter Register
CTS2 BREAK CTS2 STAT DELTA 0x0000 Description MC68VZ328 User’s Manual Setting 0 = Character has no framing error 1 = Character has a framing error 0 = Character is not a break character 1 = Character is a break character...
Page 277 Table 14-13. UART 2 Transmitter Register Description (Continued) Name FIFO FIFO Half (FIFO Status)—This read-only bit indicates that the HALF transmitter FIFO is less than half full. This bit generates a Bit 14 maskable interrupt. Transmit FIFO Has a Slot Available (FIFO Status)—This AVAIL read-only bit indicates that the transmitter FIFO has at least Bit 13...
Page 278: Uart 2 Miscellaneous Register
Reserved Reserved Bits 9–8 14-26 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFF918 Setting 0 = Normal mode. 1 = Test mode. 0 = Bit clock is generated by the baud rate generator. 1 = Bit clock is supplied by the UCLK pin.
Page 279 Table 14-14. UART 2 Miscellaneous Register Description (Continued) Name RTS2 RTS2 Control—This bit selects the function of the RTS2 pin. CONT Bit 7 RTS2 Request to Send Pin—This bit controls the RTS2 pin when Bit 6 the RTS2 CONT bit is 0. IRDAEN Infrared Enable—This bit enables the IrDA interface.
Page 280: Uart 2 Non-Integer Prescaler Register
110 = Divide range is 128 to 255 1/2 in 1/2 steps. 111 = Disable the non-integer prescaler. 0000 0000. Step = 0. 0000 0001. Step = 1. 1111 1110. Step = 254. 1111 1111. Step = 255. MC68VZ328 User’s Manual 0x(FF)FFF91A BIT 0 STEP VALUE Setting...
Page 281: Fifo Level Marker Interrupt Register
14.4.14 FIFO Level Marker Interrupt Register The UART FIFO level marker register configures the level at which either the RxFIFO or the TxFIFO reports a half-full condition. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-16. HMARK FIFO Level Marker Interrupt Register BIT 15...
Page 282: Table 14-17 Fifo Level Marker Settings
>= 40 1010 >= 44 1011 >= 48 1100 >= 52 1101 >= 56 1110 >= 60 1111 MC68VZ328 User’s Manual Number of Bytes Received Disable >= 4 >= 8 >= 12 >= 16 >= 20 >= 24 >= 28 >= 32...
Page 283: Pulse-Width Modulator 1 And 2
Chapter 15 Pulse-Width Modulator 1 and 2 This chapter describes the DragonBall VZ’s two pulse-width modulators (PWMs). Each of the pulse-width modulators has three modes of operation—playback, tone, and digital-to-analog (D/A) conversion. Using these modes, the PWM can be used to play back high-quality digital sounds, produce simple tones, or convert digital data into analog waveforms.
Page 284: Pwm Clock Signals
Figure 15-2 illustrates the block diagram of the pulse-width modulator unit 1. SYSCLK CLK32 CLKSRC Divider Prescaler 15-2 MPU Interface 5-Byte FIFO PCLK Sample Compare Counter Period Figure 15-2. PWM 1 Block Diagram MC68VZ328 User’s Manual Output PWMO Control...
Page 285: Pwm Operation
15.3 PWM Operation The pulse-width modulator has three modes of operation—playback, tone, and D/A. 15.3.1 Playback Mode In playback mode, the pulse-width modulator uses the data from a sound file to output the resulting audio through an external speaker. Although the PWM can reproduce the contents of a sound file, it is necessary to use a sampling frequency that is equal to or an even multiple of the one used to originally record the sound for the best quality reproduction.
Page 286: Programming Model
0 = The FIFO is not empty. 1 = The FIFO has one or no sample bytes remaining. 0 = The PWM interrupt is disabled (default). 1 = The PWM interrupt is enabled. MC68VZ328 User’s Manual 0x(FF)FFF500 BIT 0 FIFOAV REPEAT...
Page 287 Table 15-1. PWM 1 Control Register Description (Continued) Name Description FIFOAV FIFO Available—This bit indicates that the Bit 5 FIFO is available for at least 1 byte of sample data. Data bytes can be loaded into the FIFO as long as this bit is set. If the FIFO is loaded while this bit is cleared, the write will be ignored.
Page 288: Pwm 1 Sample Register
Sample 1—This field represents the low byte of a two-sample word. This byte will be Bits 7–0 presented to the pulse-width modulator after the SAMPLE0 field. When used with single 8-bit samples, data must be written to this byte. 15-6 PWM 1 Sample Register 0xXXXX Description MC68VZ328 User’s Manual 0x(FF)FFF502 SAMPLE1 Setting None None...
Page 289: Pwm 1 Period Register
15.4.3 PWM 1 Period Register This register controls the pulse-width modulator period. When the counter value matches PERIOD + 1, the counter is reset to start another period. Therefore, the following equation applies: PWMO (Hz) = PCLK (Hz) / (PERIOD + 2) Writing 0xFF to this register achieves the same result as writing 0xFE.
Page 290: Pwm 2
15-8 Width Compare Counter Period Compare Figure 15-4. PWM 2 Block Diagram PWM 2 Control Register LOAD 0x0000 Description MC68VZ328 User’s Manual Output PWMO Control 0x(FF)FFF510 PWMEN CLKSEL Setting 0 = No PWM period rollover. 1 = PWM period rolled over.
Page 291: Pwm 2 Period Register
Table 15-5. PWM 2 Control Register Description (Continued) Name Pin Status Indicator—This bit indicates the current status of the Bit 7 PWM. Reserved Reserved Bit 6 Output Polarity—This bit controls the PWM output polarity. Bit 5 PWMEN PWM Enable—This bit enables PWM 2. Bit 4 Reserved Reserved...
Page 292: Pwm 2 Pulse Width Register
RESET Table 15-8. PWM 2 Counter Register Description Name COUNT Count—Indicates the current counter value. Bits 15–0 15-10 WIDTH 0x0000 Description NOTE: PWM 2 Counter Register COUNT 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFF514 Setting None 0x(FF)FFF516 BIT 0 Setting None...
Page 293: In-Circuit Emulation
Chapter 16 In-Circuit Emulation This chapter describes the in-circuit emulation (ICE) module of the MC68VZ328 and provides detailed information about its operation and registers. The ICE module is designed to support low-cost emulator designs using the MC68VZ328 microprocessor. Using four interface signals that are extended to external pins, the ICE module has access to the 68000 CPU resources, with minimal restrictions.
Page 294: Ice Operation
The in-circuit emulation module latches the state of the EMUIRQ signal on the rising edge of the RESET signal. To put the MC68VZ328 in emulation mode, the EMUIRQ signal must be driven low (externally) during system reset. After system reset, EMUIRQ becomes a falling edge trigger signal, which generates a level 7 interrupt when active.
Page 295: Execution Breakpoints Vs. Bus Breakpoints
16.1.2.1 Execution Breakpoints vs. Bus Breakpoints An execution breakpoint is a breakpoint at which the current program execution stops and gives control to the monitor. To set up a single execution breakpoint, initialize the compare and mask registers; set the SB, PBEN, and CEN bits in the in-circuit emulation module control register (ICEMCR);...
Page 296: Programming Model
The register bit assignments are shown in the following register displays, and the settings of the bit assignments for both registers are described in Table 16-1 on page 16-5. 16-4 MC68VZ328 User’s Manual...
Page 297: Table 16-1 Ice Module Address Compare And Mask Registers Description
ICEMACR ICE Module Address Compare Register TYPE RESET TYPE RESET ICEMAMR ICE Module Address Mask Register TYPE RESET TYPE RESET Table 16-1. ICE Module Address Compare and Mask Registers Description Name Address Compare 31–0—These bits represent the value of the Bits 31–0 execution/bus breakpoint address.
Page 298: In-Circuit Emulation Module Control Compare And Mask Register
16-6 0x0000 Description ICE Control Mask Register 0x0000 These bits are reserved and should be set to 0. MC68VZ328 User’s Manual 0x(FF)FFFFFD08 BIT 0 Setting These bits are reserved and should be set to 0. 0 = Write cycle breakpoint.
Page 299 Table 16-3. ICE Control Mask Register Description (Continued) Name Description Read or Write Cycle Mask—This Bit 1 bit masks the RW bit of the ICEMCCR. Program or Data Cycle Bit 0 Mask—This bit masks the PD bit of the ICEMCCR. Setting 0 = Enable the comparator to compare itself against the RW bit.
Page 300: In-Circuit Emulation Module Control Register
PBEN Program Break Enable—This bit is used to select a program Bit 1 or bus break. 16-8 SWEN 0x0000 Description MC68VZ328 User’s Manual 0x(FF)FFFFFD0C BIT 0 BBIEN HMDIS PBEN Setting These bits are reserved and should be set to 0.
Page 301: Table 16-5 Emulation Mode Hard Coded Memory Locations
Table 16-4. ICE Module Control Register Description (Continued) Name Compare Enable—This bit is used to activate the compari- Bit 0 son logic. It is recommended that the address compare and mask registers be programmed before setting this bit to valid. Table 16-5.
Page 302: In-Circuit Emulation Module Status Register
Figure 16-2 on page 16-11 illustrates an example of a typical emulator design. It is a simple and low-cost design that uses the MC68VZ328 as the processor to be emulated. Other functional units include the host control to the PC or workstation via an RS-232 or a dedicated parallel interface, an optional address...
Page 303: Host Interface
PC. The monitor program is located in ROM at 0xFFFC0000–0xFFFCFFFF and is enabled or disabled by the EMUCS signal. Typical Design Programming Example MOCLK Control BUSW CSxx A[23:0] MC68VZ328 CSxx 3.3 V / 5 V Buffer DTACK D[15:0] CLKO Solder-on Emulator Pod...
Page 304: Emulation Memory Mapping Fpga And Emulation Memory
16.4 Plug-in Emulator Design Example Figure 16-3 on page 16-13 displays an example of a plug-in emulator design. The design is simple and low-cost, and it creates a very basic debugging environment. 16-12 MC68VZ328 User’s Manual...
Page 305: Figure 16-3 Plug-In Emulator Design Example
EMUCS A[15:14] EMUIRQ DTACK MC68VZ328 On-Board Memory CSxx RAM/ROM D[15:0] D[15:0] Figure 16-3. Plug-in Emulator Design Example Although there is only one hardware breakpoint in this design, all other software breakpoints can be generated by replacing the memory content of the A0 instruction. The EMUCS is decoded by a PAL to generate chip-select signals to the UART (68HC681) or ADI interface and the debug RAM or ROM or both RAM and ROM.
Page 306: Application Development Design Example
PAL decoding the EMUCS, A13, and A14 signals. The board also provides optional SRAM and ROM plug-in sockets for expansion. 16-14 1N4148 0.47 µ 0.47 µ 0.1 µ MC1455 RESET EMUCS MC68VZ328 CSxx D[15:0] MC68VZ328 User’s Manual RS-232 Host Interface 68HC681 ADI Port Debug ROM/RAM On-Board Memory RAM/ROM D[15:0] D[15:0]...
Page 307: Bootstrap Mode
This chapter describes the operation and programming information of the bootstrap mode of the MC68VZ328. The bootstrap mode is designed to allow the initialization of a target system and the ability to download programs or data to the target system RAM using either the UART 1 or UART 2 controller.
Page 308: Entering Bootstrap Mode
The 4-byte address field indicates where the data will be stored, and this address could be any MC68VZ328 internal register location. The count field of the record contains the number of data bytes to be transferred. The data field contains the data to be transferred.
Page 309: Setting Up The Rs-232 Terminal
17.1.3 Setting Up the RS-232 Terminal To set up communication between your target system and the PC, set the communication specifications to 19,200 bps, no parity, 8-bit, and 1 stop bit. It is permissible to pause after each line (b-record) is transferred to ensure that each transferred ASCII character is echoed.
Page 310: System Initialization Programming Example
FFFFF30404007FFFFF IMR The bootloader starts receiving a new b-record when a nonhexadecimal digit is received. Therefore, comments can be made in the b-record file as long as it contains no more than eight consecutive hexadecimal digits. 17-4 NOTE: MC68VZ328 User’s Manual...
Page 311: Application Programming Example
ENTER key. As long as a program execution b-record is not issued, the MC68VZ328 will remain in bootstrap mode. ;d1 is used to count the number of words copied.
Page 312: Example Of Instruction Buffer Usage
CPU registers D0–D6 and A0 are used by the bootloader program. Writing to these registers may corrupt the bootloader program. 17.2 Bootloader Flowchart The following flowchart illustrates how the bootloader program operates inside the MC68VZ328. The bootloader starts when the MC68VZ328 enters bootstrap mode. 17-6 ; instruction buffer location ;...
Page 313: Figure 17-2 Bootloader Program Operation
Start Test receive FIFO; Initialize appropriate UART Receive a bootstrap record CNT = 0? ADDR = IBUFF? Run program starting at ADDR Figure 17-2. Bootloader Program Operation Bootstrap Mode Bootloader Flowchart Store DATA to ADDR Execute instruction in IBUFF 17-7...
Page 314: Special Notes
Special Notes 17.3 Special Notes The following information may be useful when the MC68VZ328 is in bootstrap mode. • A b-record is a string of uppercase hex characters with optional comments that follow. • Comments in a b-record or b-record file must not contain any word or symbol that is longer than nine characters.
Page 315: Application Guide
18.1.2 8-Bit Bus Width Issues To ensure maximum flexibility, the MC68VZ328 supports both 8- and 16-bit data bus modes. Except the chip-select group A, which carries the boot chip select signal CSA0 and is normally connected to boot ROM, all the chip select signals are programmable to 8-bit or 16-bit mode after reset. The data bus width for the CSA0 and CSA1 signals is only controlled by the BUSW/DTACK/PG0 signal.
Page 316: Clock And Layout Considerations
This section covers layout considerations affecting DragonBall timing issues during operation and also during the initial power up. • Place the crystal within 0.5 inches of the MC68VZ328. The crystal and the capacitors must be as close to the chip as possible. •...
Page 317: Electrical Characteristics
This chapter documents electrical characteristics and provides timing information necessary to design systems using the MC68VZ328 microprocessor. Section 19.2, “DC Electrical Characteristics,” provides detailed information about both maximum and minimum DC characteristics of the MC68VZ328. Section 19.3, “AC Electrical Characteristics,” consists of output delays, input setup and hold times, and signal skew times.
Page 318: Dc Electrical Characteristics
AC Electrical Characteristics 19.2 DC Electrical Characteristics Table 19-2 contains both maximum and minimum DC characteristics of the MC68VZ328. Table 19-2. Maximum and Minimum DC Characteristics Number or Characteristic Symbol Full running operating current at 33 MHz Standby current Input high voltage...
Page 319: Chip-Select Read Cycle Timing
CLKO RASx CASx Figure 19-1. CLKO Reference to Chip-Select Signals Timing Diagram Table 19-3. CLKO Reference to Chip-Select Signals Timing Parameters Number CLKO high to CSx asserted CLKO low to CSx negated CLKO high to RASx asserted CLKO high to RASx negated CLKO high to CASx asserted CLKO high to CASx negated 19.3.2...
Page 320: Figure 19-2 Chip-Select Read Cycle Timing Diagram
UB/LB asserted to CSx asserted (16-bit SRAM) 19-4 Minimum 20, 20 - T/2 — — — 60 + nT, (60 + T/2) + nT MC68VZ328 User’s Manual (3.0 ± 0.3) V Unit Maximum — — 35 + nT 20 + nT —...
Page 321: Chip-Select Write Cycle Timing
Table 19-4. Chip-Select Read Cycle Timing Parameters (Continued) Number Characteristic CSx negated to UB/LB negated (16-bit SRAM) Note: n is the number of wait states in the current memory access cycle. T is the system clock period. The external DTACK input requirement is eliminated when CSx is programmed to use internal DTACK. CSx stands for CSA0, CSA1, CSB0, CSB1, CSC0, CSC1, CSD0, or CSD1.
Page 322: Chip-Select Flash Write Cycle Timing
Chapter 6, “Chip-Select Logic.” 19-6 Minimum 20, 20 - T/2 — — 60 + nT, (60 + T/2) + nT — MC68VZ328 User’s Manual (3.0 ± 0.3) V Unit Maximum — 20 + nT — — —...
Page 323: Figure 19-4 Chip-Select Flash Write Cycle Timing Diagram
A[31:0] UWE/LWE D[15:0] DTACK Figure 19-4. Chip-Select Flash Write Cycle Timing Diagram Table 19-6. Chip-Select Flash Write Cycle Timing Parameters Number Characteristic Address valid to CSx asserted (bit ECDS = 0, bit ECDS = 1) CSx asserted to UWE/LWE asserted CSx asserted to data-out valid External DTACK input setup from CSx asserted CSx pulse width...
Page 324: Chip-Select Timing Trim
The signal values and units of measure for this figure are found in Table 19-8 on page 19-9. Detailed information about the operation of individual signals can be found in Chapter 7, “DRAM Controller,” and Chapter 6, “Chip-Select Logic.” 19-8 Characteristic MC68VZ328 User’s Manual (3.0 ± 0.3) V Unit Minimum Maximum —...
Page 325: Figure 19-6 Dram Read Cycle 16-Bit Access (Cpu Bus Master) Timing Diagram
MD[12:0] RASx CASx D[15:0] Figure 19-6. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Diagram Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters Number Characteristic Row address valid to RASx asserted DWE negated before row address valid OE asserted before RASx is asserted RASx asserted before row address invalid (MSW = 0,1)
Page 326: Dram Write Cycle 16-Bit Access (Cpu Bus Master)
Chapter 7, “DRAM Controller,” and Chapter 6, “Chip-Select Logic.” MD[12:0] RASx CASx D[15:0] Figure 19-7. DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Diagram 19-10 Minimum 58,118 Column MC68VZ328 User’s Manual (3.0 ± 0.3) V Unit Maximum — — —...
Page 327: Dram Hidden Refresh Cycle (Normal Mode)
Table 19-9. DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Parameters Number Characteristic Row address valid to RASx asserted DWE asserted before CASx asserted OE negated before RASx asserted RASx asserted before row address invalid (MSW = 0,1) Column address valid to CASx asserted (MSW = 0,1) RASx asserted to CASx asserted (MSW = 0,1) RASx pulse width (SLW = 0,1)
Page 328: Dram Hidden Refresh Cycle (Low-Power Mode)
Table 19-11 on page 19-13. Detailed information about the operation of individual signals can be found in Chapter 7, “DRAM Controller.” CASx RASx Figure 19-9. DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Diagram 19-12 Minimum MC68VZ328 User’s Manual (3.0 ± 0.3) V Unit Maximum — — —...
Page 329: Lcd Sram/Rom Dma Cycle 16-Bit Mode Access (1 Wait State)
Table 19-11. DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Parameters Number Characteristic CASx pulse width RASx pulse width CASx asserted to RASx asserted CASx negated to RASx negated Refresh cycle (using 32.768 KHz crystal) Refresh cycle (using 38.400 KHz crystal) DWE negated before CASx asserted Note: RASx stands for RAS0 and RAS1.
Page 330: Lcd Dram Dma Cycle 16-Bit Edo Ram Mode Access (Lcd Bus Master)
CASx D[15:0] Figure 19-11. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master) 19-14 (3.0 ± 0.3) V Minimum — — Col 1 Col 2 Col 3 Timing Diagram MC68VZ328 User’s Manual Unit Maximum — — —...
Page 331: Table 19-13 Lcd Dram Dma Cycle 16-Bit Edo Ram Mode Access (Lcd Bus Master)
Table 19-13. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master) Number Characteristic Row address valid to RASx asserted DWE negated before row address valid OE asserted before RASx asserted RASx asserted before row address invalid (MSW = 0,1) Column address valid to CASx asserted (MSW = 0,1) RASx asserted to CASx asserted (MSW = 0,1)
Page 332: Lcd Dram Dma Cycle 16-Bit Fast Page Mode Access (Lcd Bus Master)
CASx asserted before column address invalid 19-16 Col 1 Col 2 Col 3 Timing Diagram Timing Parameters Minimum 12,27 10,25 28,58 MC68VZ328 User’s Manual Col n Col n+1 (3.0 ± 0.3) V Unit Maximum — — — — — —...
Page 333: Lcd Controller Timing
Table 19-14. LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master) Number Characteristic RASx pulse width CASx pulse width (BC[1:0] = 00,01,10,11 in FPM) CASx precharge time RASx negated to CASx negated Data-in hold after CASx negated OE negated after CASx negated Note: N is the number of words in one DMA transfer.
Page 334: Figure 19-14 Lcd Controller Timing Diagram (Self-Refresh Mode)
LCLK remain in inactive level. 19-18 Self-Refresh Mode (3.0 ± 0.3) V Minimum (4 * pixclk) - 2 (4 * pixclk) - 2 (2 * pixclk) - 2 MC68VZ328 User’s Manual Unit Maximum — — (2 * pixclk) + 2...
Page 335: Page-Miss Sdram Cpu Read Cycle (Cas Latency = 1)
19.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency = 1) Figure 19-15 shows the timing diagram for the page-miss SDRAM CPU read cycle. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,”...
Page 336: Mc68Vz328 User's Manual
Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.” SDCLK SCKEN A[16:1]/MD[15:0] SDA10 D[15:0] DTACK Figure 19-16. Page-Hit SDRAM CPU Read Cycle Timing Diagram 19-20 Read Command MC68VZ328 User’s Manual...
Page 337: Page-Hit Cpu Read Cycle For 8-Bit Sdram (Cas Latency = 1)
19.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency = 1) Figure 19-17 shows the timing diagram for the page-hit CPU read cycle for 8-bit SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,”...
Page 338: Page-Miss Sdram Cpu Write Cycle (Cas Latency = 1)
Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.” SDCLK SCKEN A[16:1]/MD[15:0] SDA10 D[15:0] DTACK Figure 19-18. Page-Miss SDRAM CPU Write Cycle Timing Diagram 19-22 Bank 1=All Bank Active Command Precharge Write Command Command MC68VZ328 User’s Manual...
Page 339: Page-Hit Sdram Cpu Write Cycle (Cas Latency = 1)
19.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency = 1) Figure 19-19 shows the timing diagram for the page-hit SDRAM CPU write cycle for 8-bit SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,”...
Page 340: Page-Hit Cpu Byte-Write Cycle For 8-Bit Sdram (Cas Latency = 1)
Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.” SDCLK SCKEN A[16:1]/MD[15:0] SDA10 D[15:0] DTACK Figure 19-20. Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM Timing Diagram 19-24 Upper Byte Lower Byte Write Command MC68VZ328 User’s Manual...
Page 341: Page-Hit Cpu Read Cycle In Power-Down Mode (Cas Latency = 1, Bit Apen Of Sdram Power-Down Register = 1)
19.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency = 1, Bit APEN of SDRAM Power-down Register = 1) Figure 19-21 shows the timing diagram for the page-hit CPU read cycle in power-down mode. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,”...
Page 342: Exit Self-Refresh Due To Cpu Read Cycle (Cas Latency = 1, Bit Rm Of Dram Control Register = 1)
Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.” SDCLK SCKEN A[16:1]/MD[15:0] SDA10 D[15:0] DTACK Figure 19-22. Exit Self-Refresh Due to CPU Read Cycle Timing Diagram 19-26 MC68VZ328 User’s Manual Active Command Read Command...
Page 343: Enter Self-Refresh Due To No Activity For 64 Clocks
19.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control Register = 1) Figure 19-23 shows the timing diagram for enter self-refresh due to no activity. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,”...
Page 344: Mc68Vz328 User's Manual
Figure 19-24. Page-Miss at Starting of LCD DMA for SDRAM Timing Diagram 19-28 Bank Col n Col n+1 1=All Bank Data n Data n+1 Data n+2 Data n+3 Active Read Command Command Precharge Read Command Command MC68VZ328 User’s Manual Col n+2 Col n+3 Read Command Read Command...
Page 345: Page-Miss At Start And In Middle Of Lcd Dma (Cas Latency = 1)
19.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1) Figure 19-25 shows the timing diagram for the page-miss at the start and in the middle of LCD DMA. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,”...
Page 346: Page-Hit Lcd Dma Cycle For Sdram (Cas Latency = 1)
D[15:0] DTACK Figure 19-26. Page-Hit LCD DMA Cycle for SDRAM Timing Diagram 19-30 Col n Col n+1 Col n+2 Data n Data n+1 Data n+2 Data n+3 Read Command Read Read Command Command MC68VZ328 User’s Manual Col n+3 Read Command...
Page 347 Table 19-16. Timing Parameters for Figure 19-15 Through Figure 19-26 Number Characteristic Clock high pulse time Clock low pulse time Clock high to address valid Clock high to chip-select Read to data sample latency Clock high to CAS asserted Clock high to SCKEN asserted Clock high to RAS asserted Self-refresh exit to active command asserted Clock high to WE asserted...
Page 348: Spi 1 And Spi 2 Generic Timing
19-34. Detailed information about the operation of individual signals can be found in Chapter 13, “Serial Peripheral Interface 1 and 2.” (Output) DATA_READY (Input) SCLK, MOSI, MISO Figure 19-28. SPI 1 Master Using DATA_READY Edge Trigger Timing Diagram 19-32 B n–1 B n–2 B n–3 B n–1 B n–2 B n–3 MC68VZ328 User’s Manual...
Page 349: Spi 1 Master Using Data_Ready Level Trigger
19.3.28 SPI 1 Master Using DATA_READY Level Trigger Figure 19-29 shows the timing diagram for the SPI 1 master using the DATA_READY level trigger. The signal values and units of measure for Figure 19-27 through Figure 19-32 are found in Table 19-17 on page 19-34.
Page 350: Spi 1 Slave Fifo Advanced By Ss Rising Edge
SS input pulse width Pause between data word Note: T = SPI clock period WAIT = Number of sysclk or 32.768 KHz clocks per sample period control register 19-34 Characteristic MC68VZ328 User’s Manual (3.0 ± 0.3) V Unit Minimum Maximum — 0.25T 0.25T...
Page 351: Normal Mode Timing
19.3.32 Normal Mode Timing Figure 19-33 shows the timing diagram for normal mode timing of the MC68VZ328. The signal values and units of measure for Figure 19-33 through Figure 19-35 are found in Table 19-18 on page 19-36. RESET EMUIRQ EMUBRK Figure 19-33.
Page 352: Bootstrap Mode Timing
AC Electrical Characteristics 19.3.34 Bootstrap Mode Timing Figure 19-35 shows the timing diagram for bootstrap mode timing of the MC68VZ328. The signal values and units of measure for Figure 19-33 through Figure 19-35 are found in Table 19-18. RESET EMUIRQ EMUBRK Figure 19-35.
Page 353: Mechanical Data And Ordering Information
Ordering Information Table 20-1 provides ordering information for the two package types: the 144-lead, plastic, thin quad flat package (TQFP) and the 144-lead mold array process ball grid array (MAPBGA) package. Table 20-1. MC68VZ328 Ordering Information Package Type 144-lead TQFP...
Page 354: Tqfp Pin Assignments
PE7/CTS1 V DD PG2/EMUIRQ PG3/HIZ/P/D PG4/EMUCS PG5/EMUBRK V SS V SS EXTAL XTAL LV DD V SS Figure 20-1. MC68VZ328 TQFP Pin Assignments—Top View 20-2 MC68VZ328 Top View MC68VZ328 User’s Manual V DD D0/PA0 D1/PA1 D2/PA2 D3/PA3 D4/PA4 D5/PA5 D6/PA6...
Page 355: Tqfp Package Dimensions
0.08 T L-M SECTION J1-J1 (ROT A TED 90 ) 144 PL Figure 20-2. MC68VZ328 TQFP Mechanical Drawing Mechanical Data and Ordering Information × 20 mm package, which has 0.5 mm spacing between the pads. 0.20 T L-M 4X 36 TIPS...
Page 356: Mapbga Pin Assignments
EMUIRQ EMUCS PG5/ EXTAL V SS EMUBRK PF2/ PD7/ XTAL CLKO IRQ6 PF1/ PD6/ LV DD IRQ5 IRQ3 Figure 20-3. MC68VZ328 MAPBGA Pin Assignments—Top View 20-4 MD11/ MD8/ MD5/ MD3/ MD1/ MD10/ MD7/ MD4/ MD2/ MD0/ MD9/ MD6/ PM5/ PM4/...
Page 357: Mapbga Package Dimensions
IDENTIFICATION IN THIS AREA 11 10 VIEW M-M 144X 0.25 Z X Y Figure 20-4. MC68VZ328 MAPBGA Mechanical Drawing Mechanical Data and Ordering Information × 13 mm package, which has 1 mm spacing between the DETAIL K METALIZED MARK FOR PIN 1 IDENTIFICATION...
Page 358: Pcb Finish Requirement
For a more reliable BGA assembly process, use HASL finish on PCB. EMNI AU finish is not recommended. When EMNI AU finish is used on PCB, brittle intermetallic fractures occasionally occur at the BGA pad–to–PCB pad solder joint. 20-6 MC68VZ328 User’s Manual...
Page 359 Index Numerics 16-Bit SRAM enable bit, see SR16 bit 32-bit counter, see cascaded timers 8- or 7-bit bit, see 8/7 bit 8/7 bit USTCNT1 register, 14-11 USTCNT2 register, 14-20 A[19:17] pins, 2-5 A[23:20]/PF[6:3] pins, 2-5 A0/PG1 pin, 2-5 Abbreviations, general, xxx AC electrical characteristics, see electrical characteristics ACDSLT bit, 8-17...
Page 360 19-6 read cycle timing, 19-3 timing parameters referenced to CLKO reference, 19-3 timing trim, 19-8 write cycle timing, 19-5 Chip-select enable bit, see EN bit Chip-select size field, see SIZ field CHx field, 8-14 CLK bit, 7-14 MC68VZ328 User’s Manual...
Page 361 CLK32 bit, 4-10 CLK32 clock signal crystal frequency range, 4-4 crystal oscillator circuit example, 4-4 crystal ramp-up time, 4-4 description, 4-4 CLKEN bit, 4-8 CLKM bit USTCNT1 register, 14-10 USTCNT2 register, 14-20 CLKO/PF2 pin, 2-4 CLKSEL field PWMC1 register, 15-5 PWMC2 register, 15-9 CLKSOURCE field TCTL1 register, 12-7...
Page 362 DRAMMC register, 7-12 DRCTL field, 13-6 DS toggle enable bit, see DST bit DSIZ3 bit, 6-17 DST bit, 6-20 DTACK generation, 7-7 DUPS2 bit, 6-17 DWE/UCLK/PE3 pin, 2-6 DWSO bit, 6-17 Dx field PADATA register, 10-7 PBDATA register, 10-9 MC68VZ328 User’s Manual...
Page 363 External INT2 interrupt bit, see INT2 bit External INT3 interrupt bit, see INT3 bit Extra UPSIZ bit enable bit, see EUPEN bit Features of MC68VZ328, 1-2 to 1-4 FIFO available bit, see FIFOAV bit FIFO empty (FIFO status) bit, see FIFO EMPTY bit...
Page 364 ICEMCMR register control register, see ICEMCR register status register, see ICEMSR register reset vector, 16-2 signal decoder, 16-3 signals, 2-11 trace module, 16-12 ICEMACR register, 16-5 ICEMAMR register, 16-5 ICEMCCR register, 16-6 ICEMCMR register, 16-6 MC68VZ328 User’s Manual...
Page 365 Interrupt service routine, programming considerations, 9-5 Interrupt sources, control bits, 9-10 Interrupt vector register, see IVR register Interrupts, external as edge triggered, 9-12 Introduction to MC68VZ328 bootstrap mode, 1-11 chip-select logic, 1-9 clock generation and power control modules, 1-8 component modules, 1-1...
Page 366 LCD refresh rate 9–0 field, see RRAx field LCD refresh rate adjustment register, see LRRA register LCD screen height register, see LYMAX register LCD screen starting address field, see SSAx field LCD screen starting address register, see LSSA register MC68VZ328 User’s Manual...
Page 367 Mask watchdog timer interrupt bit, see MWDT bit Master DRAM controller enable bit, see EN bit Maximum ratings, see electrical characteristics Maximum width field, see XMx field MC68VZ328–to–SDRAM connections, recommendations, 7-5 to 7-6 MEMIQ bit, 9-10 Memory map, see programmer’s memory map...
Page 368 PEPUEN register, 10-23 PERIOD field PWMP1 register, 15-7 PWMP2 register, 15-9 PESEL register, 10-23 PFDATA register, 10-25 PFDIR register, 10-24 PFPUEN register, 10-27 PFSEL register, 10-27 PGDATA register, 10-29 PGDIR register, 10-28 PGPUEN register, 10-30 PGSEL register, 10-31 MC68VZ328 User’s Manual...
Page 369 PGSZ field, 7-14 PHA bit SPICONT1 register, 13-7 SPICONT2 register, 13-16 Phase bit, see PHA bit Phase-locked loop, see PLLCLK output frequency PIN bit, 15-9 Pin status indicator bit, see PIN bit Pixel clock divider 5–0 field, see PCDx field Pixel offset code field, see POSx field Pixel polarity bit, see PIXPOL bit PIXPOL bit, 8-16...
Page 370 4-12 Programming model CGM, 4-8 to 4-10 chip-select, 6-4 to 6-21 CPU, 1-5 to 1-8 DRAM controller, 7-12 to 7-18 GP timers, 12-6 to 12-12 I/O ports, 10-6 to 10-40 ICE module, 16-4 to 16-14 MC68VZ328 User’s Manual...
Page 371 interrupt controller, 9-7 to 9-19 LCD controller, 8-10 to 8-22 PWM 1, 15-4 to 15-7 PWM 2, 15-8 to 15-10 SPI 1, 13-4 to 13-11 SPI 2, 13-14 to 13-16 system control, 5-2 to 5-6 UARTs, 14-10 to 14-30 PROT bit, 4-10 Protect bit bit, see PROT bit Pull-down field, see PDx field Pull-down resistors, see I/O ports...
Page 372 UMISC1 register, 14-17 UMISC2 register, 14-27 RXRE bit USTCNT1 register, 14-11 USTCNT2 register, 14-21 Sample 0 field, see SAMPLE0 field Sample 1 field, see SAMPLE1 field Sample repeats field, see REPEAT field SAMPLE0 field, 15-6 SAMPLE1 field, 15-6 MC68VZ328 User’s Manual...
Page 373 SB bit, 16-8 SCR register, 5-2 Screen starting address 31–1 field, see SSAx field SDRAM interface signals, 2-10 SDRAM, selecting multiplexing options, 7-5 to 7-6 SDRAM–to–MC68VZ328 connections, recommendations, 7-5 to 7-6 SELECT field NIPR1 register, 14-18 NIPR2 register, 14-28 Self-refresh mode, see LCD controller...
Page 374 Timer for real-time clock bit, see MRTI bit Timer prescaler register 1, see TPRER1 register Timer prescaler register 2, see TPRER2 register Timer signals introduction, 2-8 timer 1 input, see TOUT/TIN/PB6 pin timer 1 output, see TOUT/TIN/PB6 pin MC68VZ328 User’s Manual...
Page 375 UART clock I/O, see UCLK/DWE/PE3 pin Timer status register 1, see TSTAT1 register Timer status register 2, see TSTAT2 register TIN pin as a clock input, 12-3 transitions that trigger capture events, 12-3 TMR1 bit IPR register, 9-18 ISR register, 9-15 TMR2 bit IPR register, 9-18 ISR register, 9-14...
Page 376 CSA register, 6-8 CSB register, 6-11 CSC register, 6-13 CSD register, 6-15 EMUCS register, 6-16 XCH bit SPICONT1 register, 13-6 SPICONT2 register, 13-15 XMx field, 8-11 XTAL oscillator, see CLK32 clock signal signal pin, 2-4 YMx field, 8-12 MC68VZ328 User’s Manual...

Motorola MC68VZ328 User Manual

About this Book

Chapter 1 Introduction

Chapter 2 Signal Descriptions

Chapter 3 Memory Map

Chapter 4 Clock Generation Module and Power Control Module

Chapter 5 System Control

Chapter 6 Chip-Select Logic

Chapter 7 DRAM Controller

Chapter 8 LCD Controller

Chapter 9 Interrupt Controller

Chapter 10 I/O Ports

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Summary of Contents for Motorola MC68VZ328