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stswi
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
NB
Definition
Operation
Description
MOTOROLA
stswi
rS,rA,NB
3
4
5
6
7
19
20
21
22
23
Store String Word Immediate
if rA = 0 then EA ← 0
else EA ← (rA)
← 32
if NB = 0 then
n
← NB
else
n
r ← rS – 1
i ← 32
do while
> 0
n
if i = 32 then r ← r + 1 (mod 32)
MEM(EA, 1) ← GPR(r)[i–i + 7]
i ← i + 8
if i = 64 then i ← 32
EA ← EA + 1
←
– 1
n
n
EA is (rA|0). Let n = NB if NB ≠ 0, n = 32 if NB = 0; n is the
number of bytes to store. Let nr = CEIL( n ÷ 4); nr is the number
of registers to supply data. n consecutive bytes starting at EA are
stored from GPRs rS through rS + nr – 1. Bytes are stored left to
right from each register. The sequence of registers wraps
around through r0 if required. Under certain conditions (like
segment boundary crossing), the data alignment exception
handler may be invoked. In some implementations, this
instruction is likely to have a greater latency and take longer to
execute than a sequence of individual load or store instructions
that produce the same results.
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—stswi
8
9
10
11
12
S
24
25
26
27
28
725
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
B-137
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