Motorola MPC823e Reference Manual page 1006

After reset, the LCD controller is disabled (PON=0) in the LCD configuration and control
register (LCCR). To operate the LCD controller, you must program the LCD registers and
set the PON bit. When enabled, the FIFOs ask the DMA controller to fill them using burst
read memory cycles. When data is available in the FIFOs, it is used to index into the color
RAM to produce a grayscale or color pattern. This pattern is then shifted out by the
horizontal control block, which generates timing for each pixel on a line, including the wait
between lines (WBL). The vertical control block counts the number of lines and provides a
wait between frames (WBF) timing.
The LCD controller consists of eight main blocks:
• FIFOs
• Pixel generation
• Horizontal control
• Vertical control
• Frame control
• DMA control
• Timing control
• LCD interface
18.3.1 FIFO Control
There are two FIFOs in the LCD controller that are concatenated for single-scan displays
and used separately for dual-scan displays. Each FIFO has the capacity to hold 12 32-bit
words. When the FIFO can accept a burst, it requests a DMA controller access, which
guarantees no FIFO overflow. When the FIFO is empty before frame completion and the
DMA cannot provide data because of heavy bus loading, a FIFO underrun condition occurs.
If such a condition occurs, the display image may flicker, tear, or shift. In order to recover,
you must restart the LCD controller. It is your responsibility to make sure the LCD controller
has sufficient bus bandwidth to avoid underrun conditions. When the data is available in the
FIFOs, the frame controller initiates frame processing.
MOTOROLA MPC823e REFERENCE MANUAL
LCD Controller
18-9