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Development Capabilities and Interface
Note: When programmed to count instruction watchpoints, the last instruction that
decrements the counter to zero is treated like any other instruction breakpoint in
that it is not executed before the machine branches to the breakpoint exception
routine. As a side effect of this behavior, the value of the counter inside the
breakpoint exception routine equals 1 and not zero. When programmed to count
load/store watchpoints, the last instruction that decrements the counter to zero
is treated like any other load/store breakpoint in that it is executed before the
machine branches to the breakpoint exception routine. Therefore, the value of
the counter inside the breakpoint exception routine equals zero.
20.3.2.4 TRAP ENABLE PROGRAMMING. The trap enable bits can be programmed by
regular software (only if MSR
special development port interface. For more information, refer to Section 20.4.3.7 Trap
Enable Mode. The value used by the breakpoint generation logic is the bit-wise OR of the
software trap enable bits written using the mtspr instruction and the development port trap
enable bits that are serially shifted using the development port. The software trap enable bits
and development port trap enable bits can be read from the ICTRL and LCTRL2 registers
using the mtspr instruction. For exact bit placement, refer to Section 20.6.2.7 Load/Store
Support AND-OR Control Register and Section 20.6.2.5 Instruction Support Control
Register.
20.4 HARDWARE DEVELOPMENT SYSTEM INTERFACE
When debugging an existing system, it is sometimes helpful to be able to do so without
making any changes. Although, in some cases it is not helpful and may even make it
impossible to add load to the lines connected to the existing system.
To support this configuration, the development system interface of the core uses the
development port, which is a dedicated serial port that does not need any of the regular
system interfaces. System activity can be controlled from the development port when the
core is in debug mode. The development port is a relatively inexpensive interface that allows
the development system to operate in a lower frequency than the core's frequency. You can
also debug the core using monitor debugger software, which is described in
Section 20.5 Software Monitor Debugger.
In debug mode, the core fetches all instructions from the development port. Data can be
read from or written to the development port. This allows memory and registers to be read
and modified by a development tool (emulator) connected to the development port. For
protection purposes, two possible working modes are defined—debug mode enable and
debug mode disable. These working modes are only selected during reset. For details, refer
to Section 20.4.2.1 Debug Mode Enable vs. Debug Mode Disable.
20-20
= 0) using the mtspr instruction or on-the-fly using the
PR
MPC823e REFERENCE MANUAL
MOTOROLA
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