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MPC823e Instruction Set—mfspr
mfspr
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
SPR*
NOTE: *This is a split field.
Definition
Operation
Description
B-94
mfspr
rD,SPR
3
4
5
6
7
19
20
21
22
23
Move from Special-Purpose Register
← spr[5–9] || spr[0–4]
n
r D ← SPR(
)
n
In the PowerPC UISA, the SPR field denotes a special-purpose
register, encoded as shown in the table below. The contents of
the designated special-purpose register are placed into r D.
SPR*
DECIMAL
SPR[5–9]
1
00000
8
00000
9
00000
NOTE: *The order of the two 5-bit halves of the SPR number is reversed
compared with the actual instruction coding.
If the SPR field contains any value other than one of the values
shown in Table 9 (and the processor is in user mode), one of the
following occurs:
•
The system illegal instruction error handler is invoked.
•
The system supervisor-level instruction error handler is
invoked.
•
The results are boundedly undefined.
Other registers altered:
•
None
MPC823e REFERENCE MANUAL
8
9
10
11
12
D
24
25
26
27
28
339
REGISTER NAME
SPR[0–4]
00001
XER
01000
LR
01001
CTR
13
14
15
SPR*
29
30
31
0
MOTOROLA
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