Motorola MPC823e Reference Manual page 1339

Microprocessor for mobile computing
Table of Contents

Advertisement

data direction register (PADIR),
data register (PADAT),
open-drain (PAODR),
pin assignment register (PAPAR),
481
16-480
registers,
port B
configuration example,
16-484
operation,
16-484
pins,
registers
open-drain (PBODR),
16-485
registers,
port C
data direction register (PCDIR),
data register (PCDAT),
interrupt control register (PCINT),
16-490
operation,
pin assignment register (PCPAR),
16-490
pins,
16-492
registers,
special options register (PCSO),
port D
data direction register (PDDIR),
data register (PDDAT),
16-497
operation,
pin assignment register (PDPAR),
16-497
pins,
16-498
registers,
registers
port B
data direction (PBDIR),
data register (PBDAT),
pin assignment (PBPAR),
parallel ports
3-6
memory map,
parameter RAM
16-30
DSP,
IDMA single-buffer mode,
SCCx in ASYNC HDLC mode,
16-182
SCCx,
parameter RAM memory map
16-463
I2C controller,
16-92
IDMA,
16-18
RISC timer tables,
SCCx in Ethernet mode,
SCCx in HDLC mode,
SCCx in Transparent mode,
SCCx in UART mode,
serial peripheral interface,
SMC in GCI mode,
SMC in Transparent mode
SMC in UART mode,
universal serial bus,
parameter RAM tables
MOTOROLA
16-481
16-480
16-480
16-
16-490
16-485
16-493
16-493
16-496
16-494
16-494
16-498
16-498
16-499
16-488
16-487
16-489
16-106
16-274
16-326
16-236
16-307
16-204
16-438
16-427
16-415
16-394
16-358
MPC823e REFERENCE MANUAL
16-463
I2C controller,
16-92
IDMA,
SCCx in ASYNC HDLC mode,
SCCx in Ethernet mode,
SCCx in HDLC mode,
SCCx in Transparent mode,
SCCx in UART mode,
16-183
SCCx,
serial peripheral interface,
SMC in GCI mode,
SMC in UART and Transparent modes,
386
SMC in UART mode,
universal serial bus,
parameter RAM, structure,
16-30
parameter storage,
15-7
15-8
parity error,
,
15-8
parity, configuring,
16-195
patterns, preamble,
16-487
16-493
PBDAT,
,
16-488
PBDIR,
23-3
PBGA (definition),
16-485
PBODR,
16-489
PBPAR,
17-16
PBRx,
16-493
PCDIR,
14-2
PCI bridge (definition),
16-496
PCINT,
PCMCIA
17-1
17-1
configuration,
17-1
features,
3-1
memory map,
operation
17-8
DMA,
17-7
I/O cards,
17-8
interrupts,
memory-only cards,
17-8
power control,
reset and three-state,
17-7
operation,
17-9
programming,
registers
17-16
base (PBRx),
interface enable (PER),
interface general control register B
17-15
(PGCRB),
interface input pins (PIPR),
interface status change (PSCR),
option (PORx),
17-3
signals,
17-22
timing examples,
2-5
PCOE,
16-494
PCPAR,
16-494
PCSO,
Index
16-274
16-326
16-236
16-307
16-204
16-438
16-427
16-
16-394
16-358
16-15
17-7
17-8
17-13
17-9
17-11
17-17
Index-21

Advertisement

Table of Contents
loading

Table of Contents