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PCMCIA Interface
CBOE—Card B Output Enable
The value of this bit is always reflected on the OP2 pin. When the PCMCIA controller is in
active mode, POE_B is connected to the OP2 pin. POE_B is used to three-state the address
and strobe pins addressing the PCMCIA card slot. Refer to Section 17.3.3 The PCMCIA
Output Port Signals .
0 = POE_B is asserted if the PCMCIA controller is active.
1 = POE_B is not asserted if the PCMCIA controller is active.
CBRESET—Card B Reset
The value of this bit is always reflected on the OP3 pin. When the PCMCIA controller is in
active mode, RESET_B is connected to the OP3 pin. RESET_B is used to place the
PCMCIA card in its default (memory-only interface) state, and initiate the beginning of any
further card initialization. Refer to Section 17.3.3 The PCMCIA Output Port Signals .
0 = RESET_B is not asserted if the PCMCIA controller is active.
1 = RESET_B is asserted if the PCMCIA controller is active.
Bits 26–31—Reserved
These bits are reserved and must be set to 0.
17.5.5 PCMCIA Base Registers
The PCMCIA base registers 0–7 (PBR0-7) contain the PCMCIA base addresses for the
PCMCIA memory or I/O windows. The base registers are used in conjunction with the BSIZE
field of the corresponding PCMCIA option register to ensure valid PCMCIA accesses.
PBR0–PBR7
BIT
0
1
2
FIELD
RESET
R/W
(IMMR & 0xFFFF0000) + 0x80 (PBR0), 0x88 (PBR1), 0x90 (PBR2), 0x98 (PBR3),
ADDR
BIT
16
17
18
FIELD
RESET
R/W
(IMMR & 0xFFFF0000) + 0x80 (PBR0), 0x88 (PBR1), 0x90 (PBR2), 0x98 (PBR3),
ADDR
NOTE: — = Undefined.
PBA—PCMCIA Base Address
17-16
3
4
5
6
7
PBA
—
R/W
0xA0 (PBR4), 0xA8 (PBR5), 0xB0 (PBR6), 0xB8 (PBR7)
19
20
21
22
23
PBA
—
R/W
0xA0 (PBR4), 0xA8 (PBR5), 0xB0 (PBR6), 0xB8 (PBR7)
MPC823e REFERENCE MANUAL
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MOTOROLA
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