Motorola MPC823e Reference Manual page 1063

Development Capabilities and Interface
20.2 PROGRAM FLOW TRACKING
The MPC823e provides many options for tracking program flows that impact performance
in varying degrees. The information provided while tracking code flow can be compressed
and captured externally and then parsed by a post-processing program using the
microarchitecture defined here. The program instruction flow is visible on the external bus
when the MPC823e is programmed to operate in serialized mode and show all fetch cycles
on the external bus. When working in this mode, although tracking of the program instruction
flow is simpler, the performance of the MPC823e is much lower than when working in
regular mode. See Section 20.6.2.5 Instruction Support Control Register for more
details about programming the core to operate in this mode.
The MPC823e implements a prefetch queue combined with parallel, out-of-order, and
pipelined execution. These features, plus the fact that most fetch cycles are performed
internally from the instruction cache, increases the performance but makes it very difficult to
provide you with the real program trace. Instructions progress inside the core from fetch to
retirement. An instruction retires from the machine only after it and all preceding instructions
finish execution with no exception. Therefore, only retired instructions can be considered
a rchitecturally executed.
Reporting program trace during retirement significantly complicates visibility and increases
the die size for the two reasons—more than one instruction can retire in a clock cycle and it
is harder to report on indirect branches during retirement. Because of this, program trace is
reported during fetch and helps to reconstruct the instructions that actually retire after fetch
canceled instructions are reported. Instructions are fetched sequentially until branches
(direct or indirect), exceptions, or interrupts appear in the program flow or until a stall in
execution forces the machine to avoid fetching the next address. These instructions can be
architecturally executed or they can be canceled in any stage of the machine pipeline.
To reconstruct a program trace, you need the program code in addition to the following
MPC823e information:
• A description of the last fetched instruction (stall, sequential, branch not taken, branch
direct taken, branch indirect taken, interrupt/exception taken).
• The addresses of all indirect flow changes targets. Indirect flow changes include all
branches using the link and count registers as the target address, all interrupts/
exceptions, as well as rfi and mtmsr because it may cause a context switch.
• The number of instructions canceled on each clock.
20-2 MPC823e REFERENCE MANUAL MOTOROLA