Motorola MPC823e Reference Manual page 412

Memory Controller
UTA—UPM Transfer Acknowledge
This bit controls the state of the TA signal sampled by the external bus interface in the
current memory cycle. The TA signal is output at the rising edge of GCLK2.
0 = The TA signal is driven low on the next rising edge of GCLK2.
1 = The TA signal is driven high on the next rising edge of GCLK2.
TODT—Turn On Disable Timer
This bit controls the disable timer mechanism.
0 = The disable timer is turned off.
1 = The disable timer for the currently accessed bank is activated. This prevents a new
access to the same bank (when controlled by the UPMs) until the disable timer
expires. For example, precharge time.
LAST—Last
If this bit is set, it is the last RAM word in the program.
0 = The UPM continues executing RAM words.
1 = The service to the UPM request is completed.
15.5.4.2 RAM WORD OPERATION. This section describes how the RAM word affects the
behavior of the chip-select, byte-select, general-purpose, transfer acknowledgment signals,
as well as address multiplexing and the wait mechanism.
15.5.4.2.1 Start Addresses. Each UPM request has a special address, except for software
requests, which can start at any RAM word. Table 15-4 provides the start addresses of the
UPM RAM words for each request type.
REQUEST TO BE SERVICED
Read Single Beat Cycle (RSS)
Read Burst Cycle (RBS)
Write Single Beat Cycle (WSS)
Write Burst Cycle (WBS)
Periodic Timer Request (PTS)
Exception (EXS)
15-54
Table 15-4. Start Address Locations
MPC823e REFERENCE MANUAL
UPM START ADDRESS
0x'00
0x'08
0x'18
0x'20
0x'30
0x'3C
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