Motorola MPC823e Reference Manual page 488

Communication Processor Module
16.3.3.4 DSP MASK REGISTER. The 8-bit read/write SDMA mask register (SDMR) is
used to mask the DSP interrupts and has the same bit format as the SDSR. If a bit in the
SDMR is a 1, the corresponding interrupt in the SDSR is enabled and if it is zero, the
corresponding interrupt is masked. This register is cleared by reset.
SDMR
BIT 0
FIELD SBER
R/W R/W
RESET 0
ADDR
SBER—SDMA Channel Bus Error (SDMA function)
0 = Disable the interrupt.
1 = Enable the interrupt.
Bits 1–5—Reserved
These bits are reserved and must be set to 0.
DSP1—DSP Chain 1 Receiver Interrupt (DSP function)
0 = Disable the DSP chain 1 interrupt.
1 = Enable the DSP chain 1 interrupt.
DSP2—DSP Chain 2 Transmitter Interrupt (DSP function)
0 = Disable the DSP chain 2 interrupt.
1 = Enable the DSP chain 2 interrupt.
16-34
1 2 3
RESERVED
R/W
0
(IMMR & 0xFFFF0000) + 0x90C
MPC823e REFERENCE MANUAL
4 5 6
DSP2
R/W
0
7
DSP1
R/W
0
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