Motorola MPC823e Reference Manual page 1087

Development Capabilities and Interface
To avoid entering debug mode after reset, the DSCK pin must be negated no later than
seven clock cycles after SRESET negates to allow the processor to jump to the reset vector
and begin normal execution. When you enter debug mode immediately after reset, the DPI
bit of the interrupt cause register (ICR) is set. For details, refer to the timing diagram
illustrated in Figure 20-7.
When debug mode is disabled, all events result in regular interrupt handling. The internal
freeze signal is asserted when an enabled event occurs, regardless of whether debug mode
is enabled or disabled. The internal freeze signal is connected to all relevant internal
modules. These modules can be programmed to stop all operations in response to the
assertion of the freeze signal. For more information, refer to Section 20.5.1 Freeze
Indication (FRZ). Furthermore, the freeze indication is negated when exiting the debug
mode and Section 20.4.2.6 Exiting Debug Mode has more information on the issue.
The following list of events can cause the core to enter debug mode. Each event results in
debug mode entry if debug mode is enabled and the corresponding enable bit is set. The
reset values of the enable bits allow you to use debug mode features even when debug
enable mode is not programmed in the DER (described in Section 20.6.3.2 Debug Enable
Register).
• System reset as a result of SRESET assertion
• Checkstop
• Machine check interrupt
• Implementation specific instruction TLB miss
• Implementation specific instruction TLB error
• Implementation specific data TLB miss
• Implementation specific data TLB error
• External interrupt, recognized when MSR
• Alignment interrupt
• Program interrupt
• Floating-point unavailable interrupt
• Decrementer interrupt, recognized when MSR
• System call interrupt
• Trace asserted when in single or branch trace mode
• Implementation-dependent software emulation interrupt
• Instruction breakpoint is recognized only when MSR
masked. When breakpoints are not masked, they are always recognized.
• Load/store breakpoint is recognized only when MSR
masked. When breakpoints are not masked, they are always recognized.
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MPC823e REFERENCE MANUAL
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