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power-on reset clock (table),
4-7
reset,
SCCx in ASYNC HDLC mode,
SCCx in Ethernet mode,
14-1
system endian,
system interface unit,
TDM with dynamic frames,
TDM with static frames,
16-114
time-slot assigner,
15-19
UPMA,
15-22
UPMB,
connecting MPC823 to external peripheral,
connecting the MPC823 to an SRAM device,
connecting the MPC823 to memory device,
connecting the MPC823 to static RAM memory,
38
connecting UPM RAM array to DRAM,
connections
16-198
IrDA,
SCCx in AppleTalk mode,
to the time-slot assigner,
16-265
control byte,
16-273
control field,
16-265
control frames,
10-11
copyback mode,
core
basic instruction pipeline,
6-2
basic structure,
6-3
block diagram,
6-1
features,
6-2
instruction flow,
register unit
control registers,
6-15
register unit,
sequencer unit
external interrupt,
6-5
flow control,
interrrupt ordering,
interrupt processing,
6-7
interrupts,
issuing instructions,
precise exception model,
6-12
serialization,
6-4
sequencer unit,
6-1
core,
5-12
cost, reduction,
20-53
COUNTA,
20-54
COUNTB,
16-9
CPCR,
CPM command register,
CPM interrupt controller
16-499
configuration register (CICR),
16-501
features,
in-service register (CISR),
MOTOROLA
5-13
16-276
16-330
12-2
16-119
16-118
16-120
,
15-31
15-38
15-29
15-
15-76
16-267
16-117
6-4
6-16
6-13
6-14
6-11
6-6
6-8
16-9
16-507
16-511
MPC823e REFERENCE MANUAL
interrupt mask register (CIMR),
interrupt pending register (CIPR),
interrupt structure (illustration),
interrupt vector register (CIVR),
interrupt vectors
16-506
encoding,
16-505
interrupt vectors,
16-512
interrupts,
masking interrupts,
16-499
operation,
16-512
PC6 example,
16-507
programming,
source priorities
highest priority interrupt,
nested interrupts,
USB and SCC2 relative priority,
16-501
source priorities,
16-513
USB example,
16-1
CPM,
6-19
6-22
CR,
,
16-233
CRC (definition),
CS output configurations,
15-55
CS,
2-6
CS2,
2-6
CS3,
2-4
CS6,
2-5
CS7,
16-318
CSMA/CD,
2-10
CTS2,
2-9
2-11
CTS3,
,
15-41
cycle types,
cyclic redundancy check,
D
6-16
7-10
DAR,
,
data cache
10-2
block diagram,
cache-inhibited accesses,
10-13
coherency,
commands
CACHE LINE FLUSH,
10-13
COPYBACK,
DATA CACHE DISABLE,
DATA CACHE ENABLE,
INVALIDATE ALL,
10-13
LOCK LINE,
UNLOCK ALL,
UNLOCK LINE,
10-13
commands,
data path block diagram,
10-12
debug support,
10-1
features,
10-12
freeze,
how to enable and disable,
Index
16-510
16-509
16-500
16-512
16-504
16-502
16-504
16-502
15-29
16-233
10-12
10-13
10-13
10-13
10-13
10-13
10-13
10-3
10-13
Index-7
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