Motorola MPC823e Reference Manual page 626

Communication Processor Module
RINV—DPLL Receive Input Invert Data
This bit must be zero in HDLC bus mode.
0 = Do not invert.
1 = Invert the data before sending it to the on-chip DPLL for reception. This setting is
used to produce FM1 from FM0 and NRZI space from NRZI mark. It can also be
used in regular NRZ mode to invert the datastream.
TINV—DPLL Transmit Input Invert Data
This bit must be zero in HDLC bus mode.
0 = Do not invert.
1 = Invert the data before sending it to the on-chip DPLL for transmission. This setting
is used to produce FM1 from FM0 and NRZI space from NRZI mark. It can also be
used in regular NRZ mode to invert the datastream.
Note: In T1 applications, setting the TINV and TEND bits creates a continuously
inverted HDLC datastream.
TPL—Transmit Preamble Length
This field determines the length of the preamble configured by the TPP field.
000 = No preamble (default).
001 = 8 bits (1 byte).
010 = 16 bits (2 bytes).
011 = 32 bits (4 bytes).
100 = 48 bits (6 bytes). Select this setting for Ethernet operation.
101 = 64 bits (8 bytes).
110 = 128 bits (16 bytes).
111 = Reserved.
TPP—Transmit Preamble Pattern
This field determines the possible bit pattern that must precede the beginning of each
transmit frame. The preamble pattern is sent prior to the first flag/sync of the frame. TPP is
ignored if a serial communication controller is programmed to UART mode. The length of
the preamble is programmed in the TPL field and the preamble pattern is typically
transmitted to a receiving station that uses a DPLL for clock recovery. The receiving DPLL
uses the regular pattern of the preamble to help it lock onto the received signal in a short,
predictable time period.
00 = All zeros.
01 = Repetitive 10s. Select this setting for Ethernet operation.
10 = Repetitive 01s.
11 = All ones. Select this setting for LocalTalk operation.
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