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15.3.1.4 MEMORY COMMAND REGISTER. The memory command register (MCR)
allows you to issue commands to stimulate UPM routine execution. This capability enables
the CPU to perform special memory operations in addition to the standard read/write and
periodic timer service operations.
MCR
BIT
0
1
2
FIELD
OP
RESET
0
R/W
R/W
ADDR
BIT
16
17
18
FIELD
MB
RESET
0
R/W
R/W
ADDR
OP—Command Opcode
This field defines the operation to be executed by the user-programmable machine that is
specified in the UM field.
00 = Writes the contents of the memory data register into the RAM location indexed by
the MAD field. (WRITE command)
01 = Reads the contents of the RAM location indexed by the MAD field and stores it in
the memory data register. (READ command)
10 = Executes the RAM word in the RAM array that services one of the eight memory
banks specified in the MB field. The executed RAM word is referenced by the
MAD field. If the executed RAM word has the LAST bit set, it will be the last RAM
word executed. (RUN command)
11 = Reserved.
Bits 2–7—Reserved
These bits are reserved and must be set to 0.
UM—User Machine
This bit selects the user-programmable machine for this command.
0 = UPMA.
1 = UPMB.
Bits 9–15—Reserved
These bits are reserved and must be set to 0.
MOTOROLA
3
4
5
6
7
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x168
19
20
21
22
23
RES
MCLF
0
0
R/W
R/W
(IMMR & 0xFFFF0000) + 0x16A
MPC823e REFERENCE MANUAL
8
9
10
11
12
UM
RESERVED
0
0
R/W
R/W
24
25
26
27
28
RESERVED
0
R/W
Memory Controller
13
14
15
29
30
31
MAD
0
R/W
15-17
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