Motorola MPC823e Reference Manual page 1321

Microprocessor for mobile computing
Table of Contents

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7-9
checkstop state,
chip-select logic
updating code and programming memory
9-14
regions,
16-507
CICR,
16-510
CIMR,
16-509
CIPR,
16-511
CISR,
16-512
CIVR,
2-12
CLK,
2-8
CLK1,
2-8
CLK2,
2-9
CLK3,
2-9
CLK4,
2-6
5-16
5-19
CLKOUT,
,
,
16-197
clock glitches,
clock input to the prescaler,
5-10
clock operation,
13-7
clock skew,
clock source and configuration options, determining,
5-22
clock source and distribution (illustration),
clock, of the video controller,
5-12
clock, SPLL reference,
clocks
5-11
block diagram,
5-22
configuration,
internal clock signals
baud rate generator clock,
general system clocks,
5-21
LCD clocks,
synchronization clocks,
internal clock signals,
keys memory map,
5-14
low-power divider,
3-3
memory map,
operation
oscillators and external clock input,
system PLL
block diagram,
5-12
system PLL,
5-10
operation,
5-3
registers,
15-44
timing,
clocks and power control
5-1
features,
clocks and power control,
20-42
CMPA-D,
6-17
CMPAx,
20-43
CMPE-F,
20-44
CMPG-H,
16-196
coding,
16-266
16-335
collisions,
,
18-12
color RAM,
15-40
command
MOTOROLA
16-158
5-2
19-3
5-19
5-16
5-20
5-16
3-4
5-12
5-12
5-1
MPC823e REFERENCE MANUAL
commands
16-11
ARM IDMA,
16-100
ARM_IDMA,
9-11
CACHE DISABLE,
9-11
CACHE ENABLE,
CACHE LINE FLUSH,
16-11
CLOSE RX BD,
278
16-308
16-331
,
,
441
16-466
,
10-13
COPYBACK,
DATA CACHE DISABLE,
DATA CACHE ENABLE,
10-13
data cache,
20-38
DEBUG PORT,
16-32
DSP,
END DOWNLOAD PROCEDURE,
16-363
ENDPOINT,
ENTER HUNT MODE,
240
16-278
16-308
,
,
415
16-364
FLG,
GCI ABORT REQUEST,
16-11
GCI TIMEOUT,
GRACEFUL STOP TRANSMIT,
239
16-277
16-308
,
,
GRACEFUL STOP TX,
16-466
I2C controller,
16-100
IDMA,
16-32
INIT DSP CHAIN,
16-11
INIT DSP,
16-11
INIT IDMA,
INIT RX AND TX PARAMS,
INIT RX PARAMETERS,
278
16-308
16-331
,
,
441
16-466
,
INIT RX PARAMS,
INIT TX AND RX PARAMETERS,
INIT TX PARAMETERS,
277
16-308
16-331
,
,
441
16-466
,
16-11
INIT TX PARAMS,
16-100
INIT_IDMA,
INSTRUCTION CACHE BLOCK INVALIDATE,
9-9
9-8
instruction cache,
9-9
INVALIDATE ALL,
9-10
LOAD & LOCK,
10-13
LOCK LINE,
RESTART TRANSMIT,
277
16-308
16-331
,
,
16-11
RESTART TX,
RISC microcontroller,
16-363
RST,
15-18
15-40
RUN,
,
SCCx in ASYNC HDLC mode,
Index
10-13
16-208
16-240
16-
,
,
,
16-396
16-415
16-
,
,
,
10-13
10-13
20-40
16-11
16-207
16-
,
,
16-331
16-396
16-
,
,
,
16-11
16-207
16-
,
16-331
,
16-11
16-11
16-208
16-240
,
,
16-396
16-415
16-
,
,
,
16-11
16-430
16-207
16-239
16-
,
,
16-396
16-415
16-
,
,
,
10-13
,
16-207
16-239
16-
,
,
16-396
16-415
,
,
16-9
16-11
,
16-277
Index-3
16-

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