Motorola MPC823e Reference Manual page 1163

NOTATION/
CONVENTION
NIA Next instruction address, which is the 32-bit address of the next instruction to be executed
(the branch destination) after a successful branch. In pseudocode, a successful branch is
indicated by assigning a value to NIA. For instructions which do not branch, the next
instruction address is CIA + 4. Does not correspond to any architected register.
OEA PowerPC operating environment architecture
Rotate Rotate the contents of a register right or left n bits without masking. This operation is used
for rotate and shift instructions.
Set Bits are set to 1.
Shift Shift the contents of a register right or left n bits, clearing vacated bits (logical shift). This
operation is used for rotate and shift instructions.
SPR(x) Special-purpose register x
TRAP Invoke the system trap handler.
Undefined An undefined value. The value may vary from one implementation to another, and from
one execution to another on the same implementation.
UISA PowerPC user instruction set architecture
VEA PowerPC virtual environment architecture
The table below describes instruction field notation conventions used in this appendix.
THE ARCHITECTURE
SPECIFICATION
RA, RB, RT, RS
MOTOROLA
BA, BB, BT crb A, crb B, crb D (respectively)
D
DS
FXM
r A, r B, r D, r S (respectively)
SI
U
UI
/, //, ///
MPC823e REFERENCE MANUAL
MPC823e Instruction Set
DEFINITION
EQUIVALENT
d
ds
CRM
SIMM
IMM
UIMM
0...0 (shaded)
B-5