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srawi
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
SH
Definition
Operation
Description
MOTOROLA
srawi
rA,rS,SH (Rc = 0)
srawi.
rA,rS,SH (Rc = 1)
3
4
5
6
7
19
20
21
22
23
Shift Right Algebraic Word Immediate
← SH
n
r ← ROTL(rS, 32 –
)
n
The contents of rS are shifted right the number of bits specified
by operand SH. Bits shifted out of position 31 are lost. The
shifted value is sign-extended before being placed in rA. The
32-bit result is placed into rA. XER[CA] is set if rS contains a
negative number and any 1 bits are shifted out of position 31;
otherwise XER[CA] is cleared. A shift amount of zero causes
XER[CA] to be cleared.
The srawi instruction, followed by addze, can be used to divide
n
quickly by 2
. The setting of the CA bit, by srawi, is independent
of mode.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
XER:
Affected: CA
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—srawi
8
9
10
11
12
S
24
25
26
27
28
824
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
RC
FORM
X
B-125
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