Motorola MPC823e Reference Manual page 605

In addition to the 144kbps ISDN 2B+D channels, the GCI provides five channels for
maintenance and control functions:
• B1 is a 64kbps bearer channel
• B2 is a 64kbps bearer channel
• M is a 64kbps monitor (M) channel
• D is a 16kbps signaling channel
• C/I is a 48kbps C/I channel (includes Tand E bits)
The M channel is used to transfer data between layer 1 devices and the control unit (the
core) and the C/I channel is used to control activation/deactivation procedures or to switch
test loops by the control unit. The M and C/I channels of the GCI bus must be routed to
SMC1 or SMC2, which have modes to support the channel protocols. The MPC823e can
support any channel of the GCI bus in the primary rate by modifying the serial interface RAM
programming.
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation
since it can access each bit of the GCI separately. The current-route RAM specifies which
the bits that are supported by the interface and serial communication controller. The receiver
only receives the bits that are enabled by the serial interface RAM and the transmitter only
transmits the bits that are enabled by the serial interface RAM and does not drive L1TXD x .
Otherwise, L1TXD x is an open-drain output and must be externally pulled high.
The MPC823e supports contention detection on the D channel of the SCIT bus. When the
MPC823e has data to transmit on the D channel, it checks a SCIT bus bit that is marked with
a special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the
physical layer bus for activity on the D channel and indicates on this bit that the channel is
free. If a collision is detected on the D channel, the physical layer device sets bit 4 of C/I
channel 2 to logic high. The MPC823e then aborts its transmission and retransmits the
frame when this bit is set again. This procedure is automatically handled for the first two
buffers of a frame.
16.7.7.1 GCI ACTIVATION/DEACTIVATION PROCEDURE. In the deactivated state, the
clock pulse is disabled and the data line is at a logic one. The layer 1 device activates the
MPC823e by enabling the clock pulses and sending an indication to C/I channel 0. Using a
maskable interrupt, the MPC823e lets the core know that a valid indication has been
received in the SMC receive buffer descriptor.
When the core activates the line, the data output of L1TXDA is programmed to zero by
setting the STZ x bit in the SIMODE register. Code 0 (command timing TIM) is transmitted
on C/I channel 0 to the layer 1 device until the STZ x bit is reset. The physical layer device
resumes the clock pulses and gives an indication in C/I channel 0. The core must reset the
STZ x bit to enable data output.
MOTOROLA MPC823e REFERENCE MANUAL
Communication Processor Module
16-151