Table of Contents
Advertisement
lhzu
Assembler Syntax
BIT
0
1
2
FIELD
41
BIT
16
17
18
FIELD
Definition
Operation
Description
MOTOROLA
lhzu
rD,d(rA)
3
4
5
6
7
19
20
21
22
23
d
Load Half Word and Zero with Update
EA ← rA + EXTS(d)
rD ← (16)0 || MEM(EA, 2)
rA ← EA
EA is the sum (rA) + d. The half word in memory addressed by
EA is loaded into the low-order 16 bits of rD. The remaining bits
in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD, the
instruction form is invalid.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—lhzu
8
9
10
11
12
D
24
25
26
27
28
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
FORM
D
B-75
Advertisement
Table of Contents
