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19.3.8 Video Frame Configuration Register (Set 1)
The video frame configuration register set 1 (VFCR1) has the same structure as VFCR0,
except it belongs to set 1 and VFCR0 belongs to set 0. The value of the VPC1 and NBPL1
fields must be non-zero or an error will occur.
VFCR1
BIT
0
1
2
FIELD
SFB1 RESERVED
RESET
0
0
R/W
R/W
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
SFB1—Single Frame Buffer 1
This bit controls whether the video controller displays an image from a single frame buffer
(A) or from both frame buffers (A and B).
0 = Frame B is valid.
1 = Frame B is not valid.
Bits 1–2—Reserved
These bits are reserved and must be set to 0.
VPC1—Vertical Pixel Count 1
This field defines the number of lines for a field.
GAP1—Gap 1
This field defines the gap in the memory between the end of a line and the beginning of the
next line in full burst units. For regular noninterlace mode, this field is set to 0. For regular
interlace mode, it is set to the value in the NBPL1 field. For example, hardware pan/scroll
options in a zoomed buffer can be implemented by using the GAP1 field with an appropriate
field buffer start address.
NBPL1—Number of Bursts per Line 1
This field defines the number of bursts per line.
MOTOROLA
3
4
5
6
7
VPC1
0
R/W
(IMMR & 0xFFFF0000) + 0x81C
19
20
21
22
23
GAP1
0
R/W
(IMMR & 0xFFFF0000) + 0x81E
MPC823e REFERENCE MANUAL
Video Controller
8
9
10
11
12
24
25
26
27
28
NBPL1
0
R/W
13
14
15
GAP1
0
R/W
29
30
31
19-13
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