Motorola MPC823e Reference Manual page 665

16.9.15.9 WAKE-UP TIMER. By issuing the ENTER HUNT MODE command, you can
temporarily disable the UART receiver and make it inactive until an idle or address character
is recognized, depending on how the UM field is set in the PSMR–SCC UART register. See
Section 16.9.15.15 SCCx UART Mode Register for more information.
If the SCCx UART controller is still in the process of receiving a message that you have
already decided to discard, you can abort its reception by issuing the ENTER HUNT MODE
command. When the message is finished, the UART receiver is reenabled by finding the idle
line or the address bit of the next message, depending on how the UM field is set. When the
receiver is in sleep mode and receives a break sequence, it increments the BRKEC counter
and generates an interrupt if the BRKE or BRKS bits are enabled in the SCCM–UART
register. Refer Section 16.9.15.16 SCCx UART Receive Buffer Descriptors for more
information about the type of receive interrupt that is registered.
16.9.15.10 BREAK SUPPORT. The SCCx UART controller provides flexible break support
to the receiver. Transmitting out-of-sequence characters is also supported by the SCCx
UART controller and is normally used for the transmission of flow control characters like
XON or XOFF. This procedure is performed using the TOSEQ entry in the SCCx UART
parameter RAM.
The SCCx UART controller polls the TOSEQ character whenever the transmitter is enabled
for UART operation, including during a UART freeze operation, UART buffer transmission,
and when no buffer is ready for transmission. TOSEQ is transmitted at a higher priority than
the other characters in the transmit buffer, but does not preempt characters already in the
transmit FIFO. This means that the XON or XOFF character may not be transmitted for eight
or four character times. To reduce this latency, the TFL bit in the GSMR_H must be set to
decrease the FIFO size to one character prior to enabling the SCCx transmitter.
TOSEQ
BIT 0 1 2
FIELD RES REA
RESET 0 0
R/W R/W R/W
ADDR
Bits 0–1 and 5–6—Reserved
These bits are reserved and must be set to 0.
REA—Ready
This bit is set by the core when the character is ready for transmission and remains 1 while
the character is being transmitted. The communication processor module clears this bit after
transmission.
MOTOROLA
3 4 5 6 7
I CT RES A
0 0 0 0
R/W R/W R/W R/W
SCCX BASE + 0x4E
MPC823e REFERENCE MANUAL
Communication Processor Module
8 9 10 11 12 13
CHARSEND
0
R/W
14 15
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