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MPC823e Instruction Set—stswx
stswx
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
B-138
stswx
rS,rA,rB
3
4
5
6
7
19
20
21
22
23
Store String Word Indexed
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + (rB)
← XER[25–31]
n
r ← rS – 1
i ← 32
do while
> 0
n
if i = 32 then r ← r + 1 (mod 32)
MEM(EA, 1) ← GPR(r)[i–i + 7]
i ← i + 8
if i = 64 then i ← 32
EA ← EA + 1
←
– 1
n
n
EA is the sum (rA|0) + (rB). Let n = XER[25–31]; n is the number
of bytes to store. Let nr = CEIL( n ÷ 4); nr is the number of
registers to supply data. n consecutive bytes starting at EA are
stored from GPRs rS through rS + nr – 1. Bytes are stored left to
right from each register. The sequence of registers wraps
around through r0 if required. If n = 0, no bytes are stored. Under
certain conditions (for example, segment boundary crossing) the
data alignment exception handler may be invoked.
Note that, in some implementations, this instruction is likely to
have a greater latency and take longer to execute, perhaps
much longer, than a sequence of individual load or store
instructions that produce the same results.
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
S
24
25
26
27
28
861
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
MOTOROLA
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