Motorola MPC823e Reference Manual page 778

Communication Processor Module
When the end of the current buffer descriptor is reached and the L bit in the TX buffer
descriptor is set, the frame collision support bytes of the Ethernet frame are appended (if the
TC bit is set in the TX buffer descriptor), and TENA is negated. This notifies the EEST that
an illegal Manchester encoding must be generated to signify the end of an Ethernet frame.
After CRC transmission, the SCCx Ethernet controller writes the frame status bits into the
buffer descriptor and clears the R bit. When the end of the current buffer descriptor is
reached and the L bit is not set, only the R bit is cleared.
In either mode, an interrupt can be issued, depending on how the I bit is set in the TX buffer
descriptor. The SCCx Ethernet controller then proceeds to the next TX buffer descriptor in
the table. You can be interrupted after each frame, after each buffer, or after a specific buffer
is transmitted. The SCCx Ethernet controller can add pad characters to short frames. If the
PAD bit is set in the TX buffer descriptor, the frame is padded up to the value of the minimum
frame length register.
To rearrange the transmit queue before the communication processor module finishes
transmitting all the frames, issue the GRACEFUL STOP TRANSMIT command. This
technique can be useful for transmitting expedited data before previously linked buffers or
for error situations. When the GRACEFUL STOP TRANSMIT command is issued, the
SCCx Ethernet controller stops immediately if no transmission is in progress or it will keep
transmitting until the current frame either finishes or terminates with a collision. When the
SCCx Ethernet controller receives the RESTART TRANSMIT command, it resumes
transmission. The SCCx Ethernet controller transmits bytes least-significant bit first.
16.9.22.6 SCCx ETHERNET CHANNEL FRAME RECEPTION PROCESS. The SCCx
Ethernet receiver is designed to work with almost no intervention from the core and can
perform address recognition, CRC checking, short frame checking, maximum DMA transfer
checking, and maximum frame length checking.
When the core enables the SCCx Ethernet receiver, it enters hunt mode as soon as the
RENA signal is asserted if CLSN is negated. In hunt mode, as data is shifted into the receive
(RX) shift register one bit at a time, the contents of the register are compared to the contents
of the SYN1 field in the data synchronization register. This compare function becomes valid
a certain number of clocks after the start of the frame (depending on the NIB bits in the
PSMR–SCC Ethernet). If the two are not equal, the next bit is shifted in and the comparison
is repeated. If a double zero or double one fault is detected between bits 14 to 21 from the
start of the frame, it is rejected. If a double zero fault is detected after 21 bits from the start
of the frame and before detection of the start frame delimiter, the frame is also rejected.
When the registers match, hunt mode is terminated and character assembly begins.
When the receiver detects the first bytes of the frame, the SCCx Ethernet controller performs
address recognition functions on the frame. The receiver can receive physical (individual),
group (multicast), and broadcast addresses. SCCx Ethernet reception frame data is not
written to memory until the internal address recognition algorithm is complete, which
improves bus utilization with frames not addressed to this station.
16-324 MPC823e REFERENCE MANUAL MOTOROLA