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18.4.6 LCD Status Register
The 8-bit memory-mapped LCD status register (LCSR) is used to report certain events to
the core. When an event is recognized, the LCD controller sets the corresponding bit in this
register, regardless of the corresponding enable bit, which is located in the LCCR. A bit is
cleared by writing a 1 (writing a 0 has no effect) and more than one bit can be cleared at a
time.
LCSR
BIT
0
1
FIELD
RESET
R/W
ADDR
Bits 0–4—Reserved
These bits are reserved and must be set to 0.
BERR—Bus Error
This status bit is set if a display memory read cycle by the LCD controller FIFO is abnormally
terminated. If the EIEN bit is set in the LCCR, then an interrupt is generated to the system
interface unit at the level specified in the IRQL field of LCCR.
UN—Underrun
When this bit is set, it indicates that a FIFO underrun condition has been detected. An
underrun condition occurs when the LCD controller is empty before a frame is completed. If
the EIEN bit is set in the LCCR, then an interrupt is generated to the system interface unit
at the level specified in the IRQL field of LCCR.
EOF—End Of Frame
This status bit is set when a frame is completed and if the IEN bit in the LCCR is enabled.
Then an interrupt is generated to the system interface unit at the level specified in the IRQL
field of LCCR.
MOTOROLA
2
3
4
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x
MPC823e REFERENCE MANUAL
LCD Controller
5
6
BERR
UN
0
0
R/W
R/W
858
7
EOF
0
R/W
18-29
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