Motorola MPC823e Reference Manual page 641

Communication Processor Module
16.9.8 Handling Interrupts In the SCCs
Interrupt handling for the SCCx channel is configured on a global basis in the CPM interrupt
pending register, CPM interrupt mask register, and CPM in-service register. In each of these
registers, a bit is used to mask, enable, or report the presence of an interrupt from SCCx.
The interrupt priority between the serial communication controllers is programmable in the
CPM interrupt configuration register. Interrupts are handled by the SCC event register in
each protocol.
A number of events can cause a serial communication controller to interrupt the processor
and these events differ slightly depending on the protocol you have selected. These events
are handled independently by the SCC event and mask registers. Events that can cause
interrupts related to the CTSx and CDx modem lines are described in Section 16.14.8 Port
C Pin Functionality.
16.9.8.1 INTERRUPT HANDLING IN THE SCC EVENT REGISTER. The 16-bit memory-
mapped SCC event (SCCE) register is used to report events recognized by a serial
communication controller. When an event is recognized, the serial communication controller
sets the corresponding bit in the SCCE, regardless of the corresponding mask bit. Since
each protocol has specific requirements, the protocol-specific mode register (PSMR) is
different for each implementation.
16.9.8.2 INTERRUPT HANDLING IN THE SCC MASK REGISTER. The 16-bit, read/write
SCC mask (SCCM) register allows you to enable or disable interrupt generation using the
communication processor module for specific events in each SCCx channel. An interrupt is
only generated if the SCCx interrupts in this channel are enabled in the CPM interrupt mask
register (CIMR).
If a bit in the SCCM register is zero, the communication processor module does not proceed
with its usual interrupt handling whenever that event occurs. Anytime a bit in the SCCM
register is set, a 1 in the corresponding bit in the SCCE register sets the SCCx bit in the CPM
interrupt pending register (CIPR), which is described in Section 16.15 The CPM Interrupt
Controller. The bit format of the SCCM register is identical to that of the SCCE. Since every
SCCx protocol has specific requirements, the SCCM bits are different for each protocol.
16.9.8.3 INTERRUPT HANDLING IN THE SCC STATUS REGISTER. The 8-bit, read/
write SCC status (SCCS) register allows you to monitor real-time status conditions on the
RXDx signal. It does not show the real-time status of the CTSx and CDx pins. Their real-
time status is available in the port C parallel I/O. Since every SCCx protocol has specific
requirements, the SCCS bits are different for each protocol.
MOTOROLA MPC823e REFERENCE MANUAL 16-187