Motorola MPC823e Reference Manual page 632

Communication Processor Module
The TOD bit does not need to be set if a new TX buffer descriptor is added to the circular
queue or if other TX buffer descriptors in that queue have not finished transmitting. Once
they are finished, however, the new TX buffer descriptors are processed. The first bit of the
frame will typically be clocked out 5-6 bit times after the TOD bit has been set to 1.
TODR
BIT 0 1 2
FIELD TOD
RESET 0
R/W R/W
ADDR
TOD—Transmit on Demand
0 = Normal operation.
1 = The RISC microcontroller gives high priority to the current TX buffer descriptor and
does not wait the normal polling time to check that the TX buffer descriptor's R bit
has been set. Instead, it begins transmitting the frame. This bit is automatically
cleared after one serial clock.
Bits 1–15—Reserved
These bits are reserved and must be set to 0.
16.9.6 SCCx Buffer Descriptor Operation
Data associated with a serial communication controller channel transmitter and receiver is
stored in buffers and each buffer is referenced by a buffer descriptor that can be located
anywhere in internal memory. The MPC823e internal memory has enough space for 224
buffer descriptors (BDs) to be shared between the universal serial bus, serial
communication controllers, serial managment controllers, serial peripheral interface, and
2
I C controller. However, you must define how the buffer descriptors will be allocated to the
serial channel's transmitter or receiver. You can select 100 buffer descriptors for the SCCx
receiver or 20 buffer descriptors for the transmitter.
The buffer descriptor table forms a circular queue with a programmable length. You can
program the start address of each channel buffer descriptor table in the internal memory. In
addition, you can allocate the parameter area of an unused channel to other used channels
as buffer descriptor tables or actual buffers. See Figure 16-65 for details.
Note: The communication processor module sets all the status bits in these buffer
descriptors, but you must clear them before submitting the buffer descriptor to
the communication processor module. For example, the parity error bit is only set
when a parity error occurs.
16-178
3 4 5 6 7
RESERVED
R/W
0xA2C
MPC823e REFERENCE MANUAL
8 9 10 11 12
0
13 14 15
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