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Memory Controller
15.3.1.7 MEMORY DATA REGISTER. The memory data register (MDR) contains the data
to be written to or read from the RAM array for UPM command operations. This register must
be set up before you issue a write command to the memory command register.
MDR
BIT
0
1
2
FIELD
RESET
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
MD—Memory Data
This field contains the RAM array word.
15.3.1.8 MEMORY ADDRESS REGISTER. The memory address register (MAR) contains
an address to be output on the address lines that are controlled by the AMX field in the RAM
word of the RAM array.
MAR
BIT
0
1
2
FIELD
RESET
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
MA—Memory Address
This field contains a 32-bit address to be output on the address bus if the AMX field is equal
to 11. Refer to Section 15.5.4 The RAM Array for more information.
15-26
3
4
5
6
7
(IMMR & 0xFFFF0000) + 0x17C
19
20
21
22
23
(IMMR & 0xFFFF0000) + 0x17E
3
4
5
6
7
(IMMR & 0xFFFF0000) + 0x164
19
20
21
22
23
(IMMR & 0xFFFF0000) + 0x166
MPC823e REFERENCE MANUAL
8
9
10
11
MD
0
R/W
24
25
26
27
MD
0
R/W
8
9
10
11
MA
0
R/W
24
25
26
27
MA
0
R/W
12
13
14
15
28
29
30
31
12
13
14
15
28
29
30
31
MOTOROLA
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