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DC Electrical Characteristics
22.3.1 Layout Practices
Each V
pin on the MPC823e must be provided with a low-impedance path to the board's
CC
supply. Each GND pin must be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The V
power supply must be bypassed
CC
to ground using at least four 0.1 µ F bypass capacitors located as close as possible to the
four sides of the package. The capacitor leads and associated printed circuit traces
connecting to chip V
and GND must be kept to less than half an inch per capacitor lead.
CC
A four-layer board is recommended, employing two inner layers as V
and GND planes.
CC
All output pins on the MPC823e have fast rise and fall times. Printed circuit (PC) trace
interconnection length must be reduced to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address
and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance
calculations must consider all device loads, as well as parasitic capacitances due to the PC
traces. Attention to proper PCB layout and bypassing becomes especially critical in systems
with higher capacitive loads because these loads create higher transient currents in the V
CC
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Try to
minimize the noise levels on the PLL supply pins.
MOTOROLA
MPC823e REFERENCE MANUAL
22-3
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