Motorola MPC823e Reference Manual page 957

Communication Processor Module
16.15.2.3 NESTED INTERRUPTS. The CPM interrupt controller supports a fully nested
interrupt environment that allows a high priority interrupt from another CPM source to
suspend a lower priority interrupt service routine. This nesting is achieved by the CPM
interrupt in-service register (CISR). The CPM interrupt controller prioritizes all interrupt
sources based on their assigned priority level. The highest priority interrupt request is
presented to the core for servicing and the core acknowledges the interrupt by setting the
IACK bit in the CIVR.
After the IACK bit is set, the vector number that corresponds to this interrupt is made
available to the core in the CIVR and the interrupt request is cleared. If there are remaining
interrupt requests, they are then prioritized and another interrupt request can be presented
to the core. Upon interruption, the interrupt mask bit in the machine status register (MSR) is
cleared to disable further interrupt requests until the software is ready to handle them. Refer
to Section 6.4.1.2.1 Machine State Register for more information.
The CISR can be used to allow a higher priority interrupt within the same interrupt level to
be presented to the core before a lower priority interrupt service is completed. Each bit in
the CISR corresponds to a CPM interrupt source. When the core acknowledges the interrupt
by setting the IACK bit of the CIVR, the bits in the CISR are set by the CPM interrupt
controller for that interrupt source.
Setting the bit prevents any subsequent CPM interrupt requests at this priority level or lower,
until the servicing of the current interrupt has completed and you clear the in-service bit.
Pending interrupts for these sources are still set in the CPM interrupt controller, which
means that, in the interrupt service routine for the CPM interrupts, you can enable the core
interrupt mask to allow higher priority interrupts within this level to generate an interrupt
request. This capability provides nesting of interrupt requests for CPM interrupt level
sources.
16.15.3 Masking Interrupt Sources in the CPM
By programming the CPM interrupt mask register (CIMR), you can mask the CPM interrupts
to prevent an interrupt request to the core. Each bit in the CIMR corresponds to one of the
CPM interrupt sources. To enable an interrupt, write a 1 to the corresponding CIMR bit.
When a masked CPM interrupt source has a pending interrupt request, the corresponding
bit in the CIPR is still set, even though the interrupt is not generated to the core. By masking
all interrupt sources in the CIMR, you can implement a polling interrupt servicing scheme for
the CPM interrupts.
When a CPM interrupt source has multiple interrupting events, you can individually mask
these events by programming a mask register within that block. Table 16-46 shows the
interrupt sources that have multiple interrupting events and Figure 16-136 illustrates an
example of how the masking occurs using SCC2 as an example.
16-503 MPC823e REFERENCE MANUAL MOTOROLA