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subfc
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
subc
MOTOROLA
subfc
rD,rA,rB (OE = 0 Rc = 0)
subfc.
rD,rA,rB (OE = 0 Rc = 1)
subfco
rD,rA,rB (OE = 1 Rc = 0)
subfco.
rD,rA,rB (OE = 1 Rc = 1)
3
4
5
6
7
19
20
21
22
23
OE
Subtract from Carrying
rD ← ¬ (rA) + (rB) + 1
The sum ¬ (rA) + (rB) + 1 is placed into rD.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
The CR0 field may not reflect the "true" (infinitely precise)
result if overflow occurs (see XER below).
XER:
Affected: CA
Affected: SO, OV (if OE = 1)
Simplified mnemonics:
rD,rA,rB
equivalent to
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—subfc
8
9
10
11
12
D
24
25
26
27
28
8
subfc
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
RC
rD,rB,rA
FORM
XO
B-147
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