Motorola MPC823e Reference Manual page 1010

LCD Controller
18.3.3 Horizontal Control
The horizontal control block tracks the pixel count for one line and any additional wait
between lines. It also enables the pixel generation block by passing a signal from the vertical
control block to each line. Upon completion of the wait between lines, as indicated in the
WBL field of the LCHCR, it signals the vertical control block and activates the LOAD/HSYNC
signal to indicate the start of the next line.
18.3.4 Vertical Control
The vertical control block counts the lines and signals the horizontal control block. Upon
completion of the wait between frames, as indicated in the WBF field in the LCVCR, it
signals the frame control block and activates the FRAME/VSYNC signal to indicate the start
of the next frame.
18.3.5 Frame Control
The frame control block initializes all counters, starts the DMA, and provides signaling to the
vertical control block. The frame control block generates an end of frame signal indicator that
can be used to generate an interrupt. The end of frame interrupt can be enabled by setting
the IEN bit in the LCCR.
18.3.6 DMA Control
The DMA control block handles all data transfers to and from the FIFOs and keeps them
filled. At the appropriate time, each FIFO is filled by the DMA control block in 16-byte
transfers. Your frame buffer address must be 16-byte aligned. When the LCD controller is
initiated at reset or after an underrun condition occurs, LCD data transfers to the panel start
after five DMA read burst accesses to display memory have filled the FIFOs. See
Section 16.5.1 SDMA Bus Arbitration and Transfers for proper arbitration configuration
between the LCD controller DMA and the SDMA.
MOTOROLA MPC823e REFERENCE MANUAL 18-13