Table of Contents
Advertisement
lhaux
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
lhaux
rD,rA,rB
3
4
5
6
7
19
20
21
22
23
Load Half Word Algebraic with Update Indexed
EA ← (rA) + (rB)
rD ← EXTS(MEM(EA, 2))
rA ← EA
EA is the sum (rA) + (rB). The half word in memory addressed
by EA is loaded into the low-order 16 bits of rD. The remaining
bits in rD are filled with a copy of the most-significant bit of the
loaded half word. EA is placed into rA. If rA = 0 or rA = rD, the
instruction form is invalid.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—lhaux
8
9
10
11
12
D
24
25
26
27
28
375
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
B-71
Advertisement
Table of Contents
