Motorola MPC823e Reference Manual page 1017

LCD Controller
The following example shows a monochrome full VGA (640×480) passive display,
single-scan, 4-bit panel data bus. The LCD controller will provide 8-bit per pixel coding with
a refresh rate of 90Hz. In this example, assume a display memory cycle burst timing of (2,
1, 1, 1) for a total of five cycles per burst. It is recommended that the LCD controller use less
than 45% of the bus.
SCLK = 25MHz
FRR = 90Hz
MB = 5
BPIX = 8
COL = 640
ROW = 480
BNUM = (COL × ROW × BPIX) ÷ 128
Bus Band Width = (BNUM × FRR × MB) ÷ SCLK
Bus Band Width
18.3.10.2 BUS LATENCY. The maximum bus latency allowed in the system is given by:
Typical example using the same data from above:
Max Latency
18-20
× ×
9600 90 5
×
= ----------------------------------- 100%
6
×10
25
×
MB SCLK
Max Latency = ------------------------------------- -
×
BNUM FRR
6
× ×10
5 25
= ---------------------------- - = 145 System Clocks
×
9600 90
MPC823e REFERENCE MANUAL
= 17%
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