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Video Controller
19.1 FEATURES
The following list summarizes the features of the video controller:
• Supports Digital TFT LCD Panels and Analog NTSC/PAL Displays
• Sequential RGB, 4:4:4, and 4:2:2 YC
• CCIR-656 Compatible 8-Bit Interface Port
• Programmable Control for Horizontal Sync, Vertical Sync, Field, Blanking, Polarity, and
Timing Generation with Half-Clock Resolution
• Supports Interlace/Noninterlace Scanning Methods
• Programmable Display Active Area
• Programmable Background Color for Inactive Areas
• Smooth Switching Between Two Picture Formats
• Supports Hardware Pan/Scroll Options in a Zoomed Buffer
• Glueless Interface to Most Digital Video Encoders
• Burst Read DMA Cycles Are Used for Maximum Bus Performance
• End-of-Frame and Bus Exception Interrupt Generation
19.2 OPERATION
The video controller consists of a register set, DMA controller with FIFOs, and a video
control RAM array, as shown in Figure 19-2. The video controller RAM array provides the
proper sequencing and control signal generation needed to synchronize the datastream
through the FIFOs. The video controller, a standalone module, is programmed using a set
of configuration registers. Once the registers have been configured and the video controller
is enabled, the DMA controller initiates burst read cycles to display memory.
19-2
C
(CCIR 601) Digital Component Video Formats
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MPC823e REFERENCE MANUAL
MOTOROLA
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