Motorola MPC823e Reference Manual page 1042

Video Controller
19.3.3 Video Command Register
The 8-bit video command register (VCMR) is used to control the display format.
VCMR
BIT 0 1
FIELD
RESET
R/W
ADDR
Bits 0–5—Reserved
These bits are reserved and must be set to 0.
ASEL—Active Set Select
This bit selects one RAM array and FIFO control register set to be active for the next frame.
The current set selection is reflected in the CAS bit of the VSR.
0 = Selects RAM_0 and FIFO register set_0 as the active set.
1 = Selects RAM_1 and FIFO register set_1 as the active set.
Note: Once the ASEL bit is changed, you cannot access video RAM until the CAS bit
in the VSR reflects the change.
BD—Blank Display
When set, this bit forces the background video to be displayed and flushes the current FIFO.
0 = Display the image from the frame buffer.
1 = Force background video and flush FIFO.
19-8
2 3 4
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x806
MPC823e REFERENCE MANUAL
5 6 7
ASEL BD
0 0
R/W R/W
MOTOROLA