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Communication Processor Module
16.9.15.20 SCCx UART STATUS REGISTER.When a serial communication controller is
in UART mode, the 8-bit read-only SCCx status register is referred to as the SCCx UART
status register (SCCS–UART). Since each protocol has specific requirements, the SCCS
bits are different for each implementation. This register allows you to monitor real-time
status conditions on the RXDx pin. The real-time status of the CTSx and CDx pins are part
of the port C parallel I/O.
SCCS–UART
BIT
0
FIELD
RESET
R/W
ADDR
Bits 0–6—Reserved
These bits are reserved and must be set to 0.
ID—Idle Status
This bit is set when the RXDx pin has been a logic one for at least a full character time.
0 = The pin is not idle.
1 = The pin is idle.
16.9.15.21 SCC2 UART PROGRAMMING EXAMPLE.The following initialization
sequence is for the 9,600 baud, 8 data bits, no parity, and stop bit of the SCC2 in UART
mode assuming a 25MHz system frequency. BRG1 is used in the example. The SCC2
UART controller is configured with the RTS2, CTS2, and CD2 pins active and the CTS2 pin
is used as an automatic flow control signal.
1. Configure the port A pins to enable the TXD2 and RXD2 pins. Write PAPAR bits 13
and 12 with ones and then write the PADIR and PAODR bits 13 and 12 with zeros.
2. Configure the port C pins to enable RTS2, CTS2, and CD2. Write PCPAR bit 14 with
one and bits 9 and 8 with zeros, PCDIR bits 14, 9, and 8 with zeros, and PCSO bits 9
and 4 with ones.
3. Configure BRG1 and write 0x010144 to the BRGC1. The DIV16 bit is not used and the
divider is 162 (decimal). The resulting BRG1 clock is 16x the preferred bit rate of SCC2
in UART mode.
4. Connect the BRG1 clock to SCC2 using the serial interface. In the SICR, set the R2CS
field to 000 and the T2CS field to 000.
5. Write 0x0001 to the SDCR to set the SDMA bus arbitration level to 5.
6. Connect the SCC2 to the NMSI and clear the SC2 bit in the SICR.
16-230
1
2
3
RESERVED
0
R
(IMMR & 0xFFFF0000) + 0xA37
MPC823e REFERENCE MANUAL
4
5
6
7
ID
0
R
MOTOROLA
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