Motorola MPC823e Reference Manual page 1037

DMA INTERFACE
FIFO
FIFO
CONTROLLER
Figure 19-2. Video Controller Block Diagram
19.2.1 The Video Controller Clock
The video controller master clock source can either be the LCDCLK, which is generated by
the system interface unit, or the external video clock signal (CLK). Refer to
Section 5.2.1 System Clock and Reset Control Register and Section 5.3.4.4 The LCD
Clocks for more information. LCDCLK is derived from the SPLL. If the external video clock
is enabled by setting the CSRC bit in the VCCR, you must provide an external video clock
(CLK) at the port D input.
Note: If an external video clock (CLK) is used, then the ratio between that external
clock and GCLK1 must not be greater than 1.25:1. For example, if your system
clock is 50MHz, then the CLK input cannot exceed 62.5MHz.
MOTOROLA
U-BUS
CONFIGURATION
REGISTERS
DMA
BACKGROUND
PIXELS
ACTIVE PIXELS
MPC823e REFERENCE MANUAL
Video Controller
HSYNC
VIDEO
VSYNC
CONTROL
FIELD
RAM
BLANK
8-BIT DATA
19-3