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divwu
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
divwu
rD,rA,rB (OE = 0 Rc = 0)
divwu.
rD,rA,rB (OE = 0 Rc = 1)
divwuo
rD,rA,rB (OE = 1 Rc = 0)
divwuo.
rD,rA,rB (OE = 1 Rc = 1)
3
4
5
6
7
19
20
21
22
23
OE
Divide Word Unsigned
dividend ← ( r A)
divisor ← ( rB)
rD ← dividend ÷ divisor
The dividend is the contents of rA. The divisor is the contents of
rB. A 32-bit quotient is formed. The 32-bit quotient is placed into
rD. The remainder is not supplied as a result.
Both operands and the quotient are interpreted as unsigned
integers, except that if Rc = 1 the first three bits of CR0 field are
set by signed comparison of the result to zero. The quotient is
the unique unsigned integer that satisfies the equation—
dividend = (quotient ∗ divisor) + r (where 0 ≤ r < divisor). If an
attempt is made to perform the division—<anything> ÷ 0—then
the contents of rD are undefined as are the contents of the LT,
GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE =
1 then OV is set.
The 32-bit unsigned remainder of dividing the contents of rA by
the contents of rB can be computed as follows:
divwu
rD,rA,rB
mullw
rD,rD,rB
subf
rD,rD,rA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—divwu
8
9
10
11
12
D
24
25
26
27
28
459
# rD = quotient
# rD = quotient * divisor
# rD = remainder
13
14
15
A
29
30
31
RC
B-51
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