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MPC823e Instruction Set—dcbtst
dcbtst
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
B-46
dcbtst
rA,rB
3
4
5
6
7
00000
19
20
21
22
23
Data Cache Block Touch for Store
EA is the sum ( r A|0) + ( r B).
This instruction is a hint that performance will be improved if the
block containing the byte addressed by EA is fetched into the
data cache, because the program will probably soon store into
the addressed byte. The hint is ignored if the block is caching-
inhibited. Executing dcbtst does not cause the system
alignment error handler to be invoked.
This instruction operates as a load from the addressed byte with
respect to address translation and protection, except that no
exception occurs in the case of a translation fault or protection
violation. Also, if the referenced and changed bits are recorded,
they are recorded as if the access was a load.
The program uses dcbtst to request a cache block fetch to
guarantee that a subsequent store will be to a cached location.
The program can later execute store instructions to put data into
memory. However, the processor is not obliged to load the
addressed cache block into the data cache.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
VEA
MPC823e REFERENCE MANUAL
8
9
10
11
12
24
25
26
27
28
246
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
MOTOROLA
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