Motorola MPC823e Reference Manual page 1039

After you program the inactive RAM set and corresponding FIFO control register set, change
the ASEL bit in the VCMR to the value of the inactive set. The video controller will switch
between the currently active set and the inactive set at the boundary of the frame. The CAS
bit in the VSR reflects the currently active set.
You can also force background video frames without disturbing the video timings by setting
the BD bit in the VCMR. During this time, the FIFO is flushed and allows you to reprogram
the current FIFO buffer address pointer registers. You can also switch between the currently
active and inactive sets during this period. After clearing the BD bit, the video controller will
continue operating according to the current RAM set and FIFO control register set.
Note: If the images contain less than 24 words of data, the video controller will not have
time to change images smoothly. You must use the force background video
method described above to ensure correct operation.
19.3 REGISTER MODEL
19.3.1 Video Controller Configuration Register
The 16-bit, memory-mapped, read/write video controller configuration register (VCCR)
contains the mode and configuration bits for the video controller.
VCCR
BIT 0 1 2
FIELD
DDT DP DPF
RESET
0 0 0
R/W
R/W R/W R/W
ADDR
DDT—Data Drive Timing
This bit determines when the data changes.
0 = The video controller drives new data on the rising edge of the video clock.
1 = The video controller drives new data on the falling edge of the video clock.
DP—Data Polarity
0 = The data polarity is active high.
1 = The data polarity is active low.
MOTOROLA
3 4 5 6 7
RES IEN EIEN IRQL
0 0 0 0
R/W R/W R/W R/W
(IMMR & 0xFFFF0000) + 0x800
MPC823e REFERENCE MANUAL
Video Controller
8 9 10 11 12 13
BO AT RES CSRC VON
0 0
R/W R/W R/W
14 15
0 0 0
R/W R/W
19-5