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LCD Controller
18.3.2 Pixel Generation
The pixel generation block retrieves data from the FIFOs to generate a grayscale or color
pattern by indexing into the color RAM area of dual-port RAM. For single-scan displays, data
is fetched serially from both FIFOs. For dual-scan displays, data is fetched alternatively from
both FIFOs.
18.3.2.1 GRAYSCALE. For single-bit grayscale (monochrome), each pixel is represented
by a single bit in the frame buffer, also called the display buffer. A zero signifies pixel off and
a one signifies pixel on. For fours bits per pixel, one pixel requires four bits in the memory
that are packed together with the next four bits for the next pixel. The LCD controller can
generate a maximum of 16 grayscale levels whereby each pixel is represented by four bits
in the frame buffer. Grayscale is generated by controlling the rate in which each pixel is
turned off and on. This method is referred to as frame rate control (FRC). Turning the pixels
on and off under frame rate control may result in a low frequency pixel refresh rate to a given
pixel. This refresh rate may cause image flickering when the same gray level is found in
adjacent pixels. However, the MPC823e-implemented FRC algorithm must minimize this
flicker.
When one bit per pixel is defined, the color RAM table is used as a transparent translation
to pass the RAM data through the LCD panel interface. When you are using two bits per
pixel, the 2-bit code is indexed into the color RAM to one of four entries. Each of these four
entries can be one of 16 possible gray level codes. These four entries are then used to
determine the FRC value for that pixel. With four bits per pixel, the 4- bit code is used to
index one of 16 entries in the color RAM. The 4-bit code from the color RAM is then used to
determine one of the 16 shades generated by frame rate control. Figure 18-8 illustrates
grayscale generation.
18-10
MPC823e REFERENCE MANUAL
MOTOROLA
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