Motorola MPC823e Reference Manual page 1350

Index
2-9
SMSYN1,
2-10
SMSYN2,
2-9
SMTXD1,
2-8
SMTXD2,
soft reset configuration,
soft reset, registers affected,
software monitor debugger,
software request, initiating,
software service register,
software tablewalk routine, minimizing,
software watchdog timer block diagram,
software watchdog timer,
16-451
SPCOM,
specialized RAM memory map,
specifications (electrical),
16-433
SPI (definition),
2-9
SPICLK,
16-452
SPIE,
16-453
SPIM,
2-9
SPIMISO,
2-9
SPIMOSI,
2-9
SPISEL,
2-3
SPKROUT,
5-12
SPLL operation,
5-1
SPLL,
16-443
SPMODE,
15-38
SRAM interface,
2-6 4-3
SRESET, ,
6-16 7-9
SRR0,
,
6-16 7-9
SRR1,
,
5-13
stability, SPLL,
start address, locating,
15-54
start addresses,
START OF FRAME token,
static branch prediction,
13-33
status, of the master,
13-38
storage reservation,
10-12
store (instruction),
11-48
store,
16-115
strobes,
2-8 13-5 13-33
STS, , ,
stwcx
13-40
conditions,
13-41
failure,
13-5 13-38
stwcx,
,
12-27
SWSR,
12-26
SWT,
10-13
sync,
synchronization
in SCCx Transparent mode,
16-304
patterns,
16-305
signals,
the trace window to internal core events,
Transparent example,
synchronization clock frequency,
Index-32
4-12
6-24
20-40
15-43
12-27
11-9
12-27
12-26
3-11
22-1
15-54
16-358
6-6
16-303
20-6
16-306
5-20
MPC823e REFERENCE MANUAL
synchronous bus masters,
16-203
synchronous mode,
12-35
SYPCR,
14-1
system (definition),
system clock and reset control register,
system clock control key,
system configuration (illustration),
1-12
system design,
system integration timers memory map,
system interface unit
12-11
bus monitor,
12-2
configuration,
12-2
features,
12-28
freeze operation,
interrupts
12-7
programming,
source priority,
12-5
structure,
12-5
interrupts,
3-1
memory map,
periodic interrupt timer,
12-29
pin multiplexing,
PowerPC decrementer,
PowerPC timebase,
programming
decrementer register,
12-30
programming,
12-17
real-time clock,
software watchdog timer,
system configuration and protection registers,
12-30
12-1
system interface unit,
system phase-locked loop,
system protection control register,
15-5
system protection,
6-24
system reset interrupt,
system reset, VCCOUT,
T
13-41
TA not asserting,
2-3 13-6 13-36 15-64
TA,
, , ,
11-49
tablewalk operation,
11-5
tablewalk,
21-1
TAP (definition),
12-14
TB,
5-27
TBK,
5-27
TBREFF0K,
5-27
TBREFF1K,
12-15
TBREFL,
12-15
TBREFU,
12-16
TBSCR,
5-27
TBSCRK,
2-12
TCK,
16-321
TCLK,
15-65 15-68
,
5-3
5-27
12-4
3-3
12-6
12-22
12-12
12-14
12-13
12-26
5-1
12-35
5-17
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