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Development Capabilities and Interface
20.2.1.2.1 Back Trace. Back trace is useful when a record of the program trace is needed
before an event, such as system failure, occurs. If back trace is needed, the external
hardware must start sampling the VF and VFLS pins and the addresses of all cycles marked
with the program trace cycle attribute immediately after reset is negated. Since the
instruction show cycles programming defaults to show all out of reset, all cycles marked with
the program trace cycle attribute are visible on the external bus. VSYNC must be asserted
sometime after reset and negated when the actual event occurs. If show all is not the
preferred mode for the instruction show cycles before the event actually occurs, VSYNC
must be asserted before exiting show all mode. If the timing of the event in question is
unknown, it is possible to use cyclic buffers. After the VSYNC signal is negated, the trace
buffer contains the program flow trace of the program executed before the event in question
occurred.
20.2.1.2.2 Window Trace. This is useful when a record of the program trace between two
events is required. The VSYNC pin must be asserted between these two events. After
VSYNC is negated, the trace buffer will contain information describing the program trace of
the program executed between the two events.
20.2.1.2.3 Synchronizing the Trace Window to the Internal Core Events. The
VSYNC signal is asserted or negated using the serial interface implemented in the
development port. To synchronize the assertion or negation to an internal core event, the
internal breakpoint hardware must be used with debug mode. This method is available only
when debug mode is enabled. For more information on debug mode, refer to
Section 20.4 Hardware Development System Interface .
To synchronize the trace window to the internal core events, follow these steps:
1. Enter debug mode either straight from reset or when using a debug mode request.
2. Program the hardware to break on the event that marks the start of the trace window
using the control registers defined in Section 20.3 Generating Watchpoints And
Breakpoints .
3. Enable debug mode entry for the programmed breakpoint in the debug enable
register. See Section 20.6.3.2 Debug Enable Register for details.
4. Return to the regular code run. The hardware generates a breakpoint when the event
in question is detected and the machine enters debug mode.
5. Program the hardware to break on the event that marks the end of the trace window.
6. Assert the VSYNC signal.
7. Return to the regular code run. The first report on the VF pins is VSYNC, where VF
equals 011. The external hardware starts sampling the program trace information after
the VF pins indicate VSYNC. The hardware generates a breakpoint when the event in
question is detected and the machine enters debug mode.
8. Negate the VSYNC signal.
9. Return to the regular code run and issue an rfi instruction. The first encoding on the
VF pins is VSYNC, where VF equals 011. The external hardware stops sampling the
program trace information after recognizing VSYNC on the VF pins.
20-6
MPC823e REFERENCE MANUAL
MOTOROLA
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