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slw
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
slw
rA,rS,rB (Rc = 0)
slw.
rA,rS,rB (Rc = 1)
3
4
5
6
7
19
20
21
22
23
Shift Left Word
← rB[27-31]
n
rA ← ROTL(rS,
)
n
If bit 26 of rB = 0, the contents of rS are shifted left the number
of bits specified by rB[27–31]. Bits shifted out of position 0 are
lost. Zeros are supplied to the vacated positions on the right. The
32-bit result is placed into rA. If bit 26 of rB = 1, 32 zeros are
placed into rA.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—slw
8
9
10
11
12
S
24
25
26
27
28
24
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
RC
FORM
X
B-123
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