Bufr Attributes And Modes - Xilinx Virtex-5 FPGA User Manual

Chapter 1: Clock Resources

BUFR Attributes and Modes

Clock division in the BUFR is controlled in software through the BUFR_DIVIDE attribute.
Table 1-8
Table 1-8: BUFR_DIVIDE Attribute
Notes:
1. Location constraint is available for BUFR.
The propagation delay through BUFR is different for BUFR_DIVIDE = 1 and
BUFR_DIVIDE = BYPASS. When set to 1, the delay is slightly more than BYPASS. All other
divisors have the same delay BUFR_DIVIDE = 1. The phase relationship between the input
clock and the output clock is the same for all possible divisions except BYPASS.
The timing relationship between the inputs and output of BUFR when using the
BUFR_DIVIDE attribute is illustrated in
attribute is set to three. Sometime before this diagram CLR was asserted.
X-Ref Target - Figure 1-21
In
•
•
•
•
•
44
lists the possible values when using the BUFR_DIVIDE attribute.
Attribute Name
BUFR_DIVIDE Defines whether the output clock is a divided
version of the input clock.
1
I
CE
CLR
T
O
Figure 1-21: BUFR Timing Diagrams with BUFR_DIVIDE Values
Figure 1-21:
Before clock event 1, CE is asserted High.
After CE is asserted and time T
three rate of the input I. T
speed specification.
Note: The duty cycle is not 50/50 for odd division. The Low pulse is one cycle of I
longer.
At time event 2, CLR is asserted. After T
toggling.
At time event 3, CLR is deasserted.
At time T after clock event 4, O begins toggling again at the divided by three
BRCKO_O
rate of I.
www.xilinx.com
Description
Figure 1-21. In this example, the BUFR_DIVIDE
T
BRCKO_O BRDO_CLRO
, the output O begins toggling at the divide by
BRCKO_O
and other timing numbers are best found in the
BRCKO_O
BRDO_CLRO
Possible Values
1, 2, 3, 4, 5, 6, 7, 8
BYPASS (default)
2 3 4
T
BRCKO_O
ug190_1_21_041808
from time event 2, O stops
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009